/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "c1/c1_FrameMap.hpp"
#include "c1/c1_LIR.hpp"
#include "runtime/sharedRuntime.hpp"
#include "vmreg_sparc.inline.hpp"
// Convert stack slot to an SP offset
// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
// so we must add it in here.
int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
} else if (r_1->is_Register()) {
if (outgoing) {
} else {
}
} else {
}
} else if (r_1->is_FloatRegister()) {
opr = as_double_opr(f);
} else {
opr = as_float_opr(f);
}
}
return opr;
}
// FrameMap
//--------------------------------------------------------
// some useful constant RInfo's:
}
// returns true if reg could be smashed by a callee.
if (reg->is_double_cpu()) {
}
}
NEEDS_CLEANUP // once the new calling convention is enabled, we no
// longer need to treat I5, I4 and L0 specially
// Because the interpreter destroys caller's I5, I4 and L0,
// we must spill them before doing a Java call as we may land in
// interpreter.
}
int i=0;
// Register usage:
// O6: sp
// I6: fp
// I7: return address
// G0: zero
// G2: thread
// G7: not available
// G6: not available
// the following registers are not normally available
for (i = 0; i < nof_fpu_regs; i++) {
_fpu_regs[i] = as_FloatRegister(i);
}
_init_done = true;
for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
}
}
}
return as_FloatRegister(n)->as_VMReg();
}
return SP_opr;
}
// JSR 292
return L7_opr;
}
int java_index = 0;
for (int i = 0; i < _incoming_arguments->length(); i++) {
}
}
}