0N/A/*
1988N/A * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "c1/c1_Defs.hpp"
1879N/A#include "c1/c1_MacroAssembler.hpp"
1879N/A#include "c1/c1_Runtime1.hpp"
1879N/A#include "interpreter/interpreter.hpp"
1879N/A#include "nativeInst_sparc.hpp"
1879N/A#include "oops/compiledICHolderOop.hpp"
1879N/A#include "oops/oop.inline.hpp"
1879N/A#include "prims/jvmtiExport.hpp"
1879N/A#include "register_sparc.hpp"
1879N/A#include "runtime/sharedRuntime.hpp"
1879N/A#include "runtime/signature.hpp"
1879N/A#include "runtime/vframeArray.hpp"
1879N/A#include "vmreg_sparc.inline.hpp"
0N/A
0N/A// Implementation of StubAssembler
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry_point, int number_of_arguments) {
0N/A // for sparc changing the number of arguments doesn't change
0N/A // anything about the frame size so we'll always lie and claim that
0N/A // we are only passing 1 argument.
0N/A set_num_rt_args(1);
0N/A
0N/A assert_not_delayed();
0N/A // bang stack before going to runtime
0N/A set(-os::vm_page_size() + STACK_BIAS, G3_scratch);
0N/A st(G0, SP, G3_scratch);
0N/A
0N/A // debugging support
0N/A assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
0N/A
0N/A set_last_Java_frame(SP, noreg);
0N/A if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
0N/A save_thread(L7_thread_cache);
0N/A // do the call
0N/A call(entry_point, relocInfo::runtime_call_type);
0N/A if (!VerifyThread) {
0N/A delayed()->mov(G2_thread, O0); // pass thread as first argument
0N/A } else {
0N/A delayed()->nop(); // (thread already passed)
0N/A }
0N/A int call_offset = offset(); // offset of return address
0N/A restore_thread(L7_thread_cache);
0N/A reset_last_Java_frame();
0N/A
0N/A // check for pending exceptions
0N/A { Label L;
727N/A Address exception_addr(G2_thread, Thread::pending_exception_offset());
0N/A ld_ptr(exception_addr, Gtemp);
2664N/A br_null_short(Gtemp, pt, L);
727N/A Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
0N/A st_ptr(G0, vm_result_addr);
727N/A Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
0N/A st_ptr(G0, vm_result_addr_2);
0N/A
0N/A if (frame_size() == no_frame_size) {
0N/A // we use O7 linkage so that forward_exception_entry has the issuing PC
0N/A call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
0N/A delayed()->restore();
0N/A } else if (_stub_id == Runtime1::forward_exception_id) {
0N/A should_not_reach_here();
0N/A } else {
727N/A AddressLiteral exc(Runtime1::entry_for(Runtime1::forward_exception_id));
727N/A jump_to(exc, G4);
0N/A delayed()->nop();
0N/A }
0N/A bind(L);
0N/A }
0N/A
0N/A // get oop result if there is one and reset the value in the thread
0N/A if (oop_result1->is_valid()) { // get oop result if there is one and reset it in the thread
0N/A get_vm_result (oop_result1);
0N/A } else {
0N/A // be a little paranoid and clear the result
727N/A Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
0N/A st_ptr(G0, vm_result_addr);
0N/A }
0N/A
0N/A if (oop_result2->is_valid()) {
0N/A get_vm_result_2(oop_result2);
0N/A } else {
0N/A // be a little paranoid and clear the result
727N/A Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
0N/A st_ptr(G0, vm_result_addr_2);
0N/A }
0N/A
0N/A return call_offset;
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {
0N/A // O0 is reserved for the thread
0N/A mov(arg1, O1);
0N/A return call_RT(oop_result1, oop_result2, entry, 1);
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {
0N/A // O0 is reserved for the thread
0N/A mov(arg1, O1);
0N/A mov(arg2, O2); assert(arg2 != O1, "smashed argument");
0N/A return call_RT(oop_result1, oop_result2, entry, 2);
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {
0N/A // O0 is reserved for the thread
0N/A mov(arg1, O1);
0N/A mov(arg2, O2); assert(arg2 != O1, "smashed argument");
0N/A mov(arg3, O3); assert(arg3 != O1 && arg3 != O2, "smashed argument");
0N/A return call_RT(oop_result1, oop_result2, entry, 3);
0N/A}
0N/A
0N/A
0N/A// Implementation of Runtime1
0N/A
0N/A#define __ sasm->
0N/A
0N/Astatic int cpu_reg_save_offsets[FrameMap::nof_cpu_regs];
0N/Astatic int fpu_reg_save_offsets[FrameMap::nof_fpu_regs];
0N/Astatic int reg_save_size_in_words;
0N/Astatic int frame_size_in_bytes = -1;
0N/A
0N/Astatic OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers) {
0N/A assert(frame_size_in_bytes == __ total_frame_size_in_bytes(reg_save_size_in_words),
2168N/A "mismatch in calculation");
0N/A sasm->set_frame_size(frame_size_in_bytes / BytesPerWord);
0N/A int frame_size_in_slots = frame_size_in_bytes / sizeof(jint);
0N/A OopMap* oop_map = new OopMap(frame_size_in_slots, 0);
0N/A
0N/A int i;
0N/A for (i = 0; i < FrameMap::nof_cpu_regs; i++) {
0N/A Register r = as_Register(i);
0N/A if (r == G1 || r == G3 || r == G4 || r == G5) {
0N/A int sp_offset = cpu_reg_save_offsets[i];
0N/A oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset),
0N/A r->as_VMReg());
0N/A }
0N/A }
0N/A
0N/A if (save_fpu_registers) {
0N/A for (i = 0; i < FrameMap::nof_fpu_regs; i++) {
0N/A FloatRegister r = as_FloatRegister(i);
0N/A int sp_offset = fpu_reg_save_offsets[i];
0N/A oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset),
0N/A r->as_VMReg());
0N/A }
0N/A }
0N/A return oop_map;
0N/A}
0N/A
0N/Astatic OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = true) {
0N/A assert(frame_size_in_bytes == __ total_frame_size_in_bytes(reg_save_size_in_words),
2168N/A "mismatch in calculation");
0N/A __ save_frame_c1(frame_size_in_bytes);
0N/A
0N/A // Record volatile registers as callee-save values in an OopMap so their save locations will be
0N/A // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
0N/A // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
0N/A // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
0N/A // (as the stub's I's) when the runtime routine called by the stub creates its frame.
0N/A // OopMap frame sizes are in c2 stack slot sizes (sizeof(jint))
0N/A
0N/A int i;
0N/A for (i = 0; i < FrameMap::nof_cpu_regs; i++) {
0N/A Register r = as_Register(i);
0N/A if (r == G1 || r == G3 || r == G4 || r == G5) {
0N/A int sp_offset = cpu_reg_save_offsets[i];
0N/A __ st_ptr(r, SP, (sp_offset * BytesPerWord) + STACK_BIAS);
0N/A }
0N/A }
0N/A
0N/A if (save_fpu_registers) {
0N/A for (i = 0; i < FrameMap::nof_fpu_regs; i++) {
0N/A FloatRegister r = as_FloatRegister(i);
0N/A int sp_offset = fpu_reg_save_offsets[i];
0N/A __ stf(FloatRegisterImpl::S, r, SP, (sp_offset * BytesPerWord) + STACK_BIAS);
0N/A }
0N/A }
0N/A
0N/A return generate_oop_map(sasm, save_fpu_registers);
0N/A}
0N/A
0N/Astatic void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
0N/A for (int i = 0; i < FrameMap::nof_cpu_regs; i++) {
0N/A Register r = as_Register(i);
0N/A if (r == G1 || r == G3 || r == G4 || r == G5) {
0N/A __ ld_ptr(SP, (cpu_reg_save_offsets[i] * BytesPerWord) + STACK_BIAS, r);
0N/A }
0N/A }
0N/A
0N/A if (restore_fpu_registers) {
0N/A for (int i = 0; i < FrameMap::nof_fpu_regs; i++) {
0N/A FloatRegister r = as_FloatRegister(i);
0N/A __ ldf(FloatRegisterImpl::S, SP, (fpu_reg_save_offsets[i] * BytesPerWord) + STACK_BIAS, r);
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid Runtime1::initialize_pd() {
0N/A // compute word offsets from SP at which live (non-windowed) registers are captured by stub routines
0N/A //
0N/A // A stub routine will have a frame that is at least large enough to hold
0N/A // a register window save area (obviously) and the volatile g registers
0N/A // and floating registers. A user of save_live_registers can have a frame
0N/A // that has more scratch area in it (although typically they will use L-regs).
0N/A // in that case the frame will look like this (stack growing down)
0N/A //
0N/A // FP -> | |
0N/A // | scratch mem |
0N/A // | " " |
0N/A // --------------
0N/A // | float regs |
0N/A // | " " |
0N/A // ---------------
0N/A // | G regs |
0N/A // | " " |
0N/A // ---------------
0N/A // | abi reg. |
0N/A // | window save |
0N/A // | area |
0N/A // SP -> ---------------
0N/A //
0N/A int i;
0N/A int sp_offset = round_to(frame::register_save_words, 2); // start doubleword aligned
0N/A
0N/A // only G int registers are saved explicitly; others are found in register windows
0N/A for (i = 0; i < FrameMap::nof_cpu_regs; i++) {
0N/A Register r = as_Register(i);
0N/A if (r == G1 || r == G3 || r == G4 || r == G5) {
0N/A cpu_reg_save_offsets[i] = sp_offset;
0N/A sp_offset++;
0N/A }
0N/A }
0N/A
0N/A // all float registers are saved explicitly
0N/A assert(FrameMap::nof_fpu_regs == 32, "double registers not handled here");
0N/A for (i = 0; i < FrameMap::nof_fpu_regs; i++) {
0N/A fpu_reg_save_offsets[i] = sp_offset;
0N/A sp_offset++;
0N/A }
0N/A reg_save_size_in_words = sp_offset - frame::memory_parameter_word_sp_offset;
0N/A // this should match assembler::total_frame_size_in_bytes, which
0N/A // isn't callable from this context. It's checked by an assert when
0N/A // it's used though.
0N/A frame_size_in_bytes = align_size_up(sp_offset * wordSize, 8);
0N/A}
0N/A
0N/A
0N/AOopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
0N/A // make a frame and preserve the caller's caller-save registers
0N/A OopMap* oop_map = save_live_registers(sasm);
0N/A int call_offset;
0N/A if (!has_argument) {
0N/A call_offset = __ call_RT(noreg, noreg, target);
0N/A } else {
0N/A call_offset = __ call_RT(noreg, noreg, target, G4);
0N/A }
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A __ should_not_reach_here();
0N/A return oop_maps;
0N/A}
0N/A
0N/A
0N/AOopMapSet* Runtime1::generate_stub_call(StubAssembler* sasm, Register result, address target,
0N/A Register arg1, Register arg2, Register arg3) {
0N/A // make a frame and preserve the caller's caller-save registers
0N/A OopMap* oop_map = save_live_registers(sasm);
0N/A
0N/A int call_offset;
0N/A if (arg1 == noreg) {
0N/A call_offset = __ call_RT(result, noreg, target);
0N/A } else if (arg2 == noreg) {
0N/A call_offset = __ call_RT(result, noreg, target, arg1);
0N/A } else if (arg3 == noreg) {
0N/A call_offset = __ call_RT(result, noreg, target, arg1, arg2);
0N/A } else {
0N/A call_offset = __ call_RT(result, noreg, target, arg1, arg2, arg3);
0N/A }
0N/A OopMapSet* oop_maps = NULL;
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A restore_live_registers(sasm);
0N/A
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A
0N/A return oop_maps;
0N/A}
0N/A
0N/A
0N/AOopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
0N/A // make a frame and preserve the caller's caller-save registers
0N/A OopMap* oop_map = save_live_registers(sasm);
0N/A
0N/A // call the runtime patching routine, returns non-zero if nmethod got deopted.
0N/A int call_offset = __ call_RT(noreg, noreg, target);
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A // re-execute the patched instruction or, if the nmethod was deoptmized, return to the
0N/A // deoptimization handler entry that will cause re-execution of the current bytecode
0N/A DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
0N/A assert(deopt_blob != NULL, "deoptimization blob must have been created");
0N/A
0N/A Label no_deopt;
2664N/A __ br_null_short(O0, Assembler::pt, no_deopt);
0N/A
0N/A // return to the deoptimization handler entry for unpacking and rexecute
0N/A // if we simply returned the we'd deopt as if any call we patched had just
0N/A // returned.
0N/A
0N/A restore_live_registers(sasm);
2041N/A
2041N/A AddressLiteral dest(deopt_blob->unpack_with_reexecution());
2041N/A __ jump_to(dest, O0);
2041N/A __ delayed()->restore();
0N/A
0N/A __ bind(no_deopt);
0N/A restore_live_registers(sasm);
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A
0N/A return oop_maps;
0N/A}
0N/A
0N/AOopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
0N/A
0N/A OopMapSet* oop_maps = NULL;
0N/A // for better readability
0N/A const bool must_gc_arguments = true;
0N/A const bool dont_gc_arguments = false;
0N/A
0N/A // stub code & info for the different stubs
0N/A switch (id) {
0N/A case forward_exception_id:
0N/A {
2168N/A oop_maps = generate_handle_exception(id, sasm);
0N/A }
0N/A break;
0N/A
0N/A case new_instance_id:
0N/A case fast_new_instance_id:
0N/A case fast_new_instance_init_check_id:
0N/A {
0N/A Register G5_klass = G5; // Incoming
0N/A Register O0_obj = O0; // Outgoing
0N/A
0N/A if (id == new_instance_id) {
0N/A __ set_info("new_instance", dont_gc_arguments);
0N/A } else if (id == fast_new_instance_id) {
0N/A __ set_info("fast new_instance", dont_gc_arguments);
0N/A } else {
0N/A assert(id == fast_new_instance_init_check_id, "bad StubID");
0N/A __ set_info("fast new_instance init check", dont_gc_arguments);
0N/A }
0N/A
0N/A if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) &&
0N/A UseTLAB && FastTLABRefill) {
0N/A Label slow_path;
0N/A Register G1_obj_size = G1;
0N/A Register G3_t1 = G3;
0N/A Register G4_t2 = G4;
0N/A assert_different_registers(G5_klass, G1_obj_size, G3_t1, G4_t2);
0N/A
0N/A // Push a frame since we may do dtrace notification for the
0N/A // allocation which requires calling out and we don't want
0N/A // to stomp the real return address.
0N/A __ save_frame(0);
0N/A
0N/A if (id == fast_new_instance_init_check_id) {
0N/A // make sure the klass is initialized
3051N/A __ ldub(G5_klass, in_bytes(instanceKlass::init_state_offset()), G3_t1);
2664N/A __ cmp_and_br_short(G3_t1, instanceKlass::fully_initialized, Assembler::notEqual, Assembler::pn, slow_path);
0N/A }
0N/A#ifdef ASSERT
0N/A // assert object can be fast path allocated
0N/A {
0N/A Label ok, not_ok;
3042N/A __ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
2664N/A // make sure it's an instance (LH > 0)
2664N/A __ cmp_and_br_short(G1_obj_size, 0, Assembler::lessEqual, Assembler::pn, not_ok);
0N/A __ btst(Klass::_lh_instance_slow_path_bit, G1_obj_size);
0N/A __ br(Assembler::zero, false, Assembler::pn, ok);
0N/A __ delayed()->nop();
0N/A __ bind(not_ok);
0N/A __ stop("assert(can be fast path allocated)");
0N/A __ should_not_reach_here();
0N/A __ bind(ok);
0N/A }
0N/A#endif // ASSERT
0N/A // if we got here then the TLAB allocation failed, so try
0N/A // refilling the TLAB or allocating directly from eden.
0N/A Label retry_tlab, try_eden;
0N/A __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves G5_klass
0N/A
0N/A __ bind(retry_tlab);
0N/A
0N/A // get the instance size
3042N/A __ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
1988N/A
0N/A __ tlab_allocate(O0_obj, G1_obj_size, 0, G3_t1, slow_path);
1988N/A
0N/A __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
0N/A __ verify_oop(O0_obj);
0N/A __ mov(O0, I0);
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A
0N/A __ bind(try_eden);
0N/A // get the instance size
3042N/A __ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
0N/A __ eden_allocate(O0_obj, G1_obj_size, 0, G3_t1, G4_t2, slow_path);
2012N/A __ incr_allocated_bytes(G1_obj_size, G3_t1, G4_t2);
1988N/A
0N/A __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
0N/A __ verify_oop(O0_obj);
0N/A __ mov(O0, I0);
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A
0N/A __ bind(slow_path);
0N/A
0N/A // pop this frame so generate_stub_call can push it's own
0N/A __ restore();
0N/A }
0N/A
0N/A oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_instance), G5_klass);
0N/A // I0->O0: new instance
0N/A }
0N/A
0N/A break;
0N/A
0N/A case counter_overflow_id:
1703N/A // G4 contains bci, G5 contains method
1703N/A oop_maps = generate_stub_call(sasm, noreg, CAST_FROM_FN_PTR(address, counter_overflow), G4, G5);
0N/A break;
0N/A
0N/A case new_type_array_id:
0N/A case new_object_array_id:
0N/A {
0N/A Register G5_klass = G5; // Incoming
0N/A Register G4_length = G4; // Incoming
0N/A Register O0_obj = O0; // Outgoing
0N/A
3042N/A Address klass_lh(G5_klass, Klass::layout_helper_offset());
0N/A assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
0N/A assert(Klass::_lh_header_size_mask == 0xFF, "bytewise");
0N/A // Use this offset to pick out an individual byte of the layout_helper:
0N/A const int klass_lh_header_size_offset = ((BytesPerInt - 1) // 3 - 2 selects byte {0,1,0,0}
0N/A - Klass::_lh_header_size_shift / BitsPerByte);
0N/A
0N/A if (id == new_type_array_id) {
0N/A __ set_info("new_type_array", dont_gc_arguments);
0N/A } else {
0N/A __ set_info("new_object_array", dont_gc_arguments);
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A // assert object type is really an array of the proper kind
0N/A {
0N/A Label ok;
0N/A Register G3_t1 = G3;
0N/A __ ld(klass_lh, G3_t1);
0N/A __ sra(G3_t1, Klass::_lh_array_tag_shift, G3_t1);
0N/A int tag = ((id == new_type_array_id)
0N/A ? Klass::_lh_array_tag_type_value
0N/A : Klass::_lh_array_tag_obj_value);
2664N/A __ cmp_and_brx_short(G3_t1, tag, Assembler::equal, Assembler::pt, ok);
0N/A __ stop("assert(is an array klass)");
0N/A __ should_not_reach_here();
0N/A __ bind(ok);
0N/A }
0N/A#endif // ASSERT
0N/A
0N/A if (UseTLAB && FastTLABRefill) {
0N/A Label slow_path;
0N/A Register G1_arr_size = G1;
0N/A Register G3_t1 = G3;
0N/A Register O1_t2 = O1;
0N/A assert_different_registers(G5_klass, G4_length, G1_arr_size, G3_t1, O1_t2);
0N/A
0N/A // check that array length is small enough for fast path
0N/A __ set(C1_MacroAssembler::max_array_allocation_length, G3_t1);
2664N/A __ cmp_and_br_short(G4_length, G3_t1, Assembler::greaterUnsigned, Assembler::pn, slow_path);
0N/A
0N/A // if we got here then the TLAB allocation failed, so try
0N/A // refilling the TLAB or allocating directly from eden.
0N/A Label retry_tlab, try_eden;
0N/A __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves G4_length and G5_klass
0N/A
0N/A __ bind(retry_tlab);
0N/A
0N/A // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
0N/A __ ld(klass_lh, G3_t1);
0N/A __ sll(G4_length, G3_t1, G1_arr_size);
0N/A __ srl(G3_t1, Klass::_lh_header_size_shift, G3_t1);
0N/A __ and3(G3_t1, Klass::_lh_header_size_mask, G3_t1);
0N/A __ add(G1_arr_size, G3_t1, G1_arr_size);
0N/A __ add(G1_arr_size, MinObjAlignmentInBytesMask, G1_arr_size); // align up
0N/A __ and3(G1_arr_size, ~MinObjAlignmentInBytesMask, G1_arr_size);
0N/A
0N/A __ tlab_allocate(O0_obj, G1_arr_size, 0, G3_t1, slow_path); // preserves G1_arr_size
0N/A
0N/A __ initialize_header(O0_obj, G5_klass, G4_length, G3_t1, O1_t2);
0N/A __ ldub(klass_lh, G3_t1, klass_lh_header_size_offset);
0N/A __ sub(G1_arr_size, G3_t1, O1_t2); // body length
0N/A __ add(O0_obj, G3_t1, G3_t1); // body start
0N/A __ initialize_body(G3_t1, O1_t2);
0N/A __ verify_oop(O0_obj);
0N/A __ retl();
0N/A __ delayed()->nop();
0N/A
0N/A __ bind(try_eden);
0N/A // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
0N/A __ ld(klass_lh, G3_t1);
0N/A __ sll(G4_length, G3_t1, G1_arr_size);
0N/A __ srl(G3_t1, Klass::_lh_header_size_shift, G3_t1);
0N/A __ and3(G3_t1, Klass::_lh_header_size_mask, G3_t1);
0N/A __ add(G1_arr_size, G3_t1, G1_arr_size);
0N/A __ add(G1_arr_size, MinObjAlignmentInBytesMask, G1_arr_size);
0N/A __ and3(G1_arr_size, ~MinObjAlignmentInBytesMask, G1_arr_size);
0N/A
0N/A __ eden_allocate(O0_obj, G1_arr_size, 0, G3_t1, O1_t2, slow_path); // preserves G1_arr_size
2012N/A __ incr_allocated_bytes(G1_arr_size, G3_t1, O1_t2);
0N/A
0N/A __ initialize_header(O0_obj, G5_klass, G4_length, G3_t1, O1_t2);
0N/A __ ldub(klass_lh, G3_t1, klass_lh_header_size_offset);
0N/A __ sub(G1_arr_size, G3_t1, O1_t2); // body length
0N/A __ add(O0_obj, G3_t1, G3_t1); // body start
0N/A __ initialize_body(G3_t1, O1_t2);
0N/A __ verify_oop(O0_obj);
0N/A __ retl();
0N/A __ delayed()->nop();
0N/A
0N/A __ bind(slow_path);
0N/A }
0N/A
0N/A if (id == new_type_array_id) {
0N/A oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_type_array), G5_klass, G4_length);
0N/A } else {
0N/A oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_object_array), G5_klass, G4_length);
0N/A }
0N/A // I0 -> O0: new array
0N/A }
0N/A break;
0N/A
0N/A case new_multi_array_id:
0N/A { // O0: klass
0N/A // O1: rank
0N/A // O2: address of 1st dimension
0N/A __ set_info("new_multi_array", dont_gc_arguments);
0N/A oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_multi_array), I0, I1, I2);
0N/A // I0 -> O0: new multi array
0N/A }
0N/A break;
0N/A
0N/A case register_finalizer_id:
0N/A {
0N/A __ set_info("register_finalizer", dont_gc_arguments);
0N/A
0N/A // load the klass and check the has finalizer flag
0N/A Label register_finalizer;
0N/A Register t = O1;
1909N/A __ load_klass(O0, t);
3042N/A __ ld(t, in_bytes(Klass::access_flags_offset()), t);
0N/A __ set(JVM_ACC_HAS_FINALIZER, G3);
0N/A __ andcc(G3, t, G0);
0N/A __ br(Assembler::notZero, false, Assembler::pt, register_finalizer);
0N/A __ delayed()->nop();
0N/A
0N/A // do a leaf return
0N/A __ retl();
0N/A __ delayed()->nop();
0N/A
0N/A __ bind(register_finalizer);
0N/A OopMap* oop_map = save_live_registers(sasm);
0N/A int call_offset = __ call_RT(noreg, noreg,
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), I0);
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A // Now restore all the live registers
0N/A restore_live_registers(sasm);
0N/A
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A }
0N/A break;
0N/A
0N/A case throw_range_check_failed_id:
0N/A { __ set_info("range_check_failed", dont_gc_arguments); // arguments will be discarded
0N/A // G4: index
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_index_exception_id:
0N/A { __ set_info("index_range_check_failed", dont_gc_arguments); // arguments will be discarded
0N/A // G4: index
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_div0_exception_id:
0N/A { __ set_info("throw_div0_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
0N/A }
0N/A break;
0N/A
0N/A case throw_null_pointer_exception_id:
0N/A { __ set_info("throw_null_pointer_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
0N/A }
0N/A break;
0N/A
0N/A case handle_exception_id:
2168N/A { __ set_info("handle_exception", dont_gc_arguments);
2168N/A oop_maps = generate_handle_exception(id, sasm);
2168N/A }
2168N/A break;
0N/A
2168N/A case handle_exception_from_callee_id:
2168N/A { __ set_info("handle_exception_from_callee", dont_gc_arguments);
2168N/A oop_maps = generate_handle_exception(id, sasm);
0N/A }
0N/A break;
0N/A
0N/A case unwind_exception_id:
0N/A {
0N/A // O0: exception
0N/A // I7: address of call to this method
0N/A
0N/A __ set_info("unwind_exception", dont_gc_arguments);
0N/A __ mov(Oexception, Oexception->after_save());
0N/A __ add(I7, frame::pc_return_offset, Oissuing_pc->after_save());
0N/A
0N/A __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address),
1295N/A G2_thread, Oissuing_pc->after_save());
0N/A __ verify_not_null_oop(Oexception->after_save());
1484N/A
2168N/A // Restore SP from L7 if the exception PC is a method handle call site.
1484N/A __ mov(O0, G5); // Save the target address.
1484N/A __ lduw(Address(G2_thread, JavaThread::is_method_handle_return_offset()), L0);
1484N/A __ tst(L0); // Condition codes are preserved over the restore.
1484N/A __ restore();
1484N/A
1484N/A __ jmp(G5, 0);
1484N/A __ delayed()->movcc(Assembler::notZero, false, Assembler::icc, L7_mh_SP_save, SP); // Restore SP if required.
0N/A }
0N/A break;
0N/A
0N/A case throw_array_store_exception_id:
0N/A {
0N/A __ set_info("throw_array_store_exception", dont_gc_arguments);
2053N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_class_cast_exception_id:
0N/A {
0N/A // G4: object
0N/A __ set_info("throw_class_cast_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_incompatible_class_change_error_id:
0N/A {
0N/A __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
0N/A }
0N/A break;
0N/A
0N/A case slow_subtype_check_id:
0N/A { // Support for uint StubRoutine::partial_subtype_check( Klass sub, Klass super );
0N/A // Arguments :
0N/A //
0N/A // ret : G3
0N/A // sub : G3, argument, destroyed
0N/A // super: G1, argument, not changed
0N/A // raddr: O7, blown by call
644N/A Label miss;
0N/A
0N/A __ save_frame(0); // Blow no registers!
0N/A
644N/A __ check_klass_subtype_slow_path(G3, G1, L0, L1, L2, L4, NULL, &miss);
0N/A
0N/A __ mov(1, G3);
644N/A __ ret(); // Result in G5 is 'true'
0N/A __ delayed()->restore(); // free copy or add can go here
0N/A
0N/A __ bind(miss);
0N/A __ mov(0, G3);
644N/A __ ret(); // Result in G5 is 'false'
0N/A __ delayed()->restore(); // free copy or add can go here
0N/A }
0N/A
0N/A case monitorenter_nofpu_id:
0N/A case monitorenter_id:
0N/A { // G4: object
0N/A // G5: lock address
0N/A __ set_info("monitorenter", dont_gc_arguments);
0N/A
0N/A int save_fpu_registers = (id == monitorenter_id);
0N/A // make a frame and preserve the caller's caller-save registers
0N/A OopMap* oop_map = save_live_registers(sasm, save_fpu_registers);
0N/A
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), G4, G5);
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A restore_live_registers(sasm, save_fpu_registers);
0N/A
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A }
0N/A break;
0N/A
0N/A case monitorexit_nofpu_id:
0N/A case monitorexit_id:
0N/A { // G4: lock address
0N/A // note: really a leaf routine but must setup last java sp
0N/A // => use call_RT for now (speed can be improved by
0N/A // doing last java sp setup manually)
0N/A __ set_info("monitorexit", dont_gc_arguments);
0N/A
0N/A int save_fpu_registers = (id == monitorexit_id);
0N/A // make a frame and preserve the caller's caller-save registers
0N/A OopMap* oop_map = save_live_registers(sasm, save_fpu_registers);
0N/A
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), G4);
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A restore_live_registers(sasm, save_fpu_registers);
0N/A
0N/A __ ret();
0N/A __ delayed()->restore();
2886N/A }
2886N/A break;
0N/A
2886N/A case deoptimize_id:
2886N/A {
2886N/A __ set_info("deoptimize", dont_gc_arguments);
2886N/A OopMap* oop_map = save_live_registers(sasm);
2886N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
2886N/A oop_maps = new OopMapSet();
2886N/A oop_maps->add_gc_map(call_offset, oop_map);
2886N/A restore_live_registers(sasm);
2886N/A DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
2886N/A assert(deopt_blob != NULL, "deoptimization blob must have been created");
2886N/A AddressLiteral dest(deopt_blob->unpack_with_reexecution());
2886N/A __ jump_to(dest, O0);
2886N/A __ delayed()->restore();
0N/A }
0N/A break;
0N/A
0N/A case access_field_patching_id:
0N/A { __ set_info("access_field_patching", dont_gc_arguments);
0N/A oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
0N/A }
0N/A break;
0N/A
0N/A case load_klass_patching_id:
0N/A { __ set_info("load_klass_patching", dont_gc_arguments);
0N/A oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
0N/A }
0N/A break;
0N/A
0N/A case dtrace_object_alloc_id:
0N/A { // O0: object
0N/A __ set_info("dtrace_object_alloc", dont_gc_arguments);
0N/A // we can't gc here so skip the oopmap but make sure that all
0N/A // the live registers get saved.
0N/A save_live_registers(sasm);
0N/A
0N/A __ save_thread(L7_thread_cache);
0N/A __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc),
0N/A relocInfo::runtime_call_type);
0N/A __ delayed()->mov(I0, O0);
0N/A __ restore_thread(L7_thread_cache);
0N/A
0N/A restore_live_registers(sasm);
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A }
0N/A break;
0N/A
342N/A#ifndef SERIALGC
342N/A case g1_pre_barrier_slow_id:
342N/A { // G4: previous value of memory
342N/A BarrierSet* bs = Universe::heap()->barrier_set();
342N/A if (bs->kind() != BarrierSet::G1SATBCTLogging) {
342N/A __ save_frame(0);
342N/A __ set((int)id, O1);
342N/A __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), I0);
342N/A __ should_not_reach_here();
342N/A break;
342N/A }
342N/A
342N/A __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
342N/A
342N/A Register pre_val = G4;
342N/A Register tmp = G1_scratch;
342N/A Register tmp2 = G3_scratch;
342N/A
342N/A Label refill, restart;
342N/A bool with_frame = false; // I don't know if we can do with-frame.
342N/A int satb_q_index_byte_offset =
342N/A in_bytes(JavaThread::satb_mark_queue_offset() +
342N/A PtrQueue::byte_offset_of_index());
342N/A int satb_q_buf_byte_offset =
342N/A in_bytes(JavaThread::satb_mark_queue_offset() +
342N/A PtrQueue::byte_offset_of_buf());
2722N/A
342N/A __ bind(restart);
2722N/A // Load the index into the SATB buffer. PtrQueue::_index is a
2722N/A // size_t so ld_ptr is appropriate
342N/A __ ld_ptr(G2_thread, satb_q_index_byte_offset, tmp);
342N/A
2722N/A // index == 0?
2722N/A __ cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pn, refill);
342N/A
2722N/A __ ld_ptr(G2_thread, satb_q_buf_byte_offset, tmp2);
342N/A __ sub(tmp, oopSize, tmp);
342N/A
342N/A __ st_ptr(pre_val, tmp2, tmp); // [_buf + index] := <address_of_card>
342N/A // Use return-from-leaf
342N/A __ retl();
342N/A __ delayed()->st_ptr(tmp, G2_thread, satb_q_index_byte_offset);
342N/A
342N/A __ bind(refill);
342N/A __ save_frame(0);
342N/A
342N/A __ mov(pre_val, L0);
342N/A __ mov(tmp, L1);
342N/A __ mov(tmp2, L2);
342N/A
342N/A __ call_VM_leaf(L7_thread_cache,
342N/A CAST_FROM_FN_PTR(address,
342N/A SATBMarkQueueSet::handle_zero_index_for_thread),
342N/A G2_thread);
342N/A
342N/A __ mov(L0, pre_val);
342N/A __ mov(L1, tmp);
342N/A __ mov(L2, tmp2);
342N/A
342N/A __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
342N/A __ delayed()->restore();
342N/A }
342N/A break;
342N/A
342N/A case g1_post_barrier_slow_id:
342N/A {
342N/A BarrierSet* bs = Universe::heap()->barrier_set();
342N/A if (bs->kind() != BarrierSet::G1SATBCTLogging) {
342N/A __ save_frame(0);
342N/A __ set((int)id, O1);
342N/A __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), I0);
342N/A __ should_not_reach_here();
342N/A break;
342N/A }
342N/A
342N/A __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
342N/A
342N/A Register addr = G4;
342N/A Register cardtable = G5;
342N/A Register tmp = G1_scratch;
342N/A Register tmp2 = G3_scratch;
342N/A jbyte* byte_map_base = ((CardTableModRefBS*)bs)->byte_map_base;
342N/A
342N/A Label not_already_dirty, restart, refill;
342N/A
342N/A#ifdef _LP64
342N/A __ srlx(addr, CardTableModRefBS::card_shift, addr);
342N/A#else
342N/A __ srl(addr, CardTableModRefBS::card_shift, addr);
342N/A#endif
342N/A
727N/A AddressLiteral rs(byte_map_base);
727N/A __ set(rs, cardtable); // cardtable := <card table base>
342N/A __ ldub(addr, cardtable, tmp); // tmp := [addr + cardtable]
342N/A
2722N/A assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
2722N/A __ cmp_and_br_short(tmp, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
342N/A
342N/A // We didn't take the branch, so we're already dirty: return.
342N/A // Use return-from-leaf
342N/A __ retl();
342N/A __ delayed()->nop();
342N/A
342N/A // Not dirty.
342N/A __ bind(not_already_dirty);
2722N/A
2722N/A // Get cardtable + tmp into a reg by itself
2722N/A __ add(addr, cardtable, tmp2);
2722N/A
342N/A // First, dirty it.
342N/A __ stb(G0, tmp2, 0); // [cardPtr] := 0 (i.e., dirty).
342N/A
342N/A Register tmp3 = cardtable;
342N/A Register tmp4 = tmp;
342N/A
342N/A // these registers are now dead
342N/A addr = cardtable = tmp = noreg;
342N/A
342N/A int dirty_card_q_index_byte_offset =
342N/A in_bytes(JavaThread::dirty_card_queue_offset() +
342N/A PtrQueue::byte_offset_of_index());
342N/A int dirty_card_q_buf_byte_offset =
342N/A in_bytes(JavaThread::dirty_card_queue_offset() +
342N/A PtrQueue::byte_offset_of_buf());
2722N/A
342N/A __ bind(restart);
2722N/A
2722N/A // Get the index into the update buffer. PtrQueue::_index is
2722N/A // a size_t so ld_ptr is appropriate here.
342N/A __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, tmp3);
342N/A
2722N/A // index == 0?
2722N/A __ cmp_and_brx_short(tmp3, G0, Assembler::equal, Assembler::pn, refill);
2722N/A
2722N/A __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, tmp4);
342N/A __ sub(tmp3, oopSize, tmp3);
342N/A
342N/A __ st_ptr(tmp2, tmp4, tmp3); // [_buf + index] := <address_of_card>
342N/A // Use return-from-leaf
342N/A __ retl();
342N/A __ delayed()->st_ptr(tmp3, G2_thread, dirty_card_q_index_byte_offset);
342N/A
342N/A __ bind(refill);
342N/A __ save_frame(0);
342N/A
342N/A __ mov(tmp2, L0);
342N/A __ mov(tmp3, L1);
342N/A __ mov(tmp4, L2);
342N/A
342N/A __ call_VM_leaf(L7_thread_cache,
342N/A CAST_FROM_FN_PTR(address,
342N/A DirtyCardQueueSet::handle_zero_index_for_thread),
342N/A G2_thread);
342N/A
342N/A __ mov(L0, tmp2);
342N/A __ mov(L1, tmp3);
342N/A __ mov(L2, tmp4);
342N/A
342N/A __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
342N/A __ delayed()->restore();
342N/A }
342N/A break;
342N/A#endif // !SERIALGC
342N/A
0N/A default:
0N/A { __ set_info("unimplemented entry", dont_gc_arguments);
0N/A __ save_frame(0);
0N/A __ set((int)id, O1);
0N/A __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), O1);
0N/A __ should_not_reach_here();
0N/A }
0N/A break;
0N/A }
0N/A return oop_maps;
0N/A}
0N/A
0N/A
2168N/AOopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
2168N/A __ block_comment("generate_handle_exception");
2168N/A
2168N/A // Save registers, if required.
2168N/A OopMapSet* oop_maps = new OopMapSet();
2168N/A OopMap* oop_map = NULL;
2168N/A switch (id) {
2168N/A case forward_exception_id:
2168N/A // We're handling an exception in the context of a compiled frame.
2168N/A // The registers have been saved in the standard places. Perform
2168N/A // an exception lookup in the caller and dispatch to the handler
2168N/A // if found. Otherwise unwind and dispatch to the callers
2168N/A // exception handler.
2168N/A oop_map = generate_oop_map(sasm, true);
2168N/A
2168N/A // transfer the pending exception to the exception_oop
2168N/A __ ld_ptr(G2_thread, in_bytes(JavaThread::pending_exception_offset()), Oexception);
2168N/A __ ld_ptr(Oexception, 0, G0);
2168N/A __ st_ptr(G0, G2_thread, in_bytes(JavaThread::pending_exception_offset()));
2168N/A __ add(I7, frame::pc_return_offset, Oissuing_pc);
2168N/A break;
2168N/A case handle_exception_id:
2168N/A // At this point all registers MAY be live.
2168N/A oop_map = save_live_registers(sasm);
2168N/A __ mov(Oexception->after_save(), Oexception);
2168N/A __ mov(Oissuing_pc->after_save(), Oissuing_pc);
2168N/A break;
2168N/A case handle_exception_from_callee_id:
2168N/A // At this point all registers except exception oop (Oexception)
2168N/A // and exception pc (Oissuing_pc) are dead.
2168N/A oop_map = new OopMap(frame_size_in_bytes / sizeof(jint), 0);
2168N/A sasm->set_frame_size(frame_size_in_bytes / BytesPerWord);
2168N/A __ save_frame_c1(frame_size_in_bytes);
2168N/A __ mov(Oexception->after_save(), Oexception);
2168N/A __ mov(Oissuing_pc->after_save(), Oissuing_pc);
2168N/A break;
2168N/A default: ShouldNotReachHere();
2168N/A }
0N/A
0N/A __ verify_not_null_oop(Oexception);
0N/A
0N/A // save the exception and issuing pc in the thread
2168N/A __ st_ptr(Oexception, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
0N/A __ st_ptr(Oissuing_pc, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
0N/A
2168N/A // use the throwing pc as the return address to lookup (has bci & oop map)
0N/A __ mov(Oissuing_pc, I7);
0N/A __ sub(I7, frame::pc_return_offset, I7);
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
2168N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A // Note: if nmethod has been deoptimized then regardless of
0N/A // whether it had a handler or not we will deoptimize
0N/A // by entering the deopt blob with a pending exception.
0N/A
2168N/A // Restore the registers that were saved at the beginning, remove
2168N/A // the frame and jump to the exception handler.
2168N/A switch (id) {
2168N/A case forward_exception_id:
2168N/A case handle_exception_id:
2168N/A restore_live_registers(sasm);
2168N/A __ jmp(O0, 0);
2168N/A __ delayed()->restore();
2168N/A break;
2168N/A case handle_exception_from_callee_id:
2168N/A // Restore SP from L7 if the exception PC is a method handle call site.
2168N/A __ mov(O0, G5); // Save the target address.
2168N/A __ lduw(Address(G2_thread, JavaThread::is_method_handle_return_offset()), L0);
2168N/A __ tst(L0); // Condition codes are preserved over the restore.
2168N/A __ restore();
0N/A
2168N/A __ jmp(G5, 0); // jump to the exception handler
2168N/A __ delayed()->movcc(Assembler::notZero, false, Assembler::icc, L7_mh_SP_save, SP); // Restore SP if required.
2168N/A break;
2168N/A default: ShouldNotReachHere();
2168N/A }
0N/A
2168N/A return oop_maps;
0N/A}
0N/A
0N/A
0N/A#undef __
0N/A
1601N/Aconst char *Runtime1::pd_name_for_address(address entry) {
1601N/A return "<unknown function>";
1601N/A}