/illumos-gate/usr/src/uts/common/io/audio/drv/audiop16x/ |
H A D | audiop16x.c | 145 write_reg(p16x_dev_t *dev, int reg, int chn, unsigned int value) function 239 write_reg(dev, CRFA, 0, 0); 240 write_reg(dev, CRCAV, 0, 0); 246 write_reg(dev, PTBA, i, 0); 247 write_reg(dev, PTBS, i, 0); 248 write_reg(dev, PTCA, i, 0); 249 write_reg(dev, PFEA, i, 0); 250 write_reg(dev, CPFA, i, 0); 251 write_reg(dev, CPCAV, i, 0); 499 write_reg(de [all...] |
/illumos-gate/usr/src/uts/common/io/e1000api/ |
H A D | e1000_82541.c | 106 phy->ops.write_reg = e1000_write_phy_reg_igp; 713 ret_val = phy->ops.write_reg(hw, 744 ret_val = phy->ops.write_reg(hw, 768 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 774 ret_val = phy->ops.write_reg(hw, 0x0000, 788 ret_val = phy->ops.write_reg(hw, 795 ret_val = phy->ops.write_reg(hw, 0x0000, 803 ret_val = phy->ops.write_reg(hw, 0x2F5B, 825 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 831 ret_val = phy->ops.write_reg(h [all...] |
H A D | e1000_phy.c | 93 phy->ops.write_reg = e1000_null_write_reg; 265 if (!hw->phy.ops.write_reg) 268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1214 ret_val = phy->ops.write_reg(h [all...] |
H A D | e1000_82575.c | 207 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 214 phy->ops.write_reg = e1000_write_phy_reg_82580; 219 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 223 phy->ops.write_reg = e1000_write_phy_reg_igp; 257 ret_val = phy->ops.write_reg(hw, 777 if (!(hw->phy.ops.write_reg)) 784 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 828 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 837 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 843 ret_val = phy->ops.write_reg(h [all...] |
H A D | e1000_82540.c | 84 phy->ops.write_reg = e1000_write_phy_reg_m88; 435 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 513 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, 544 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 559 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 572 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 605 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 611 ret_val = hw->phy.ops.write_reg(h [all...] |
H A D | e1000_80003es2lan.c | 122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1098 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1175 ret_val = hw->phy.ops.write_reg(h [all...] |
H A D | e1000_82543.c | 116 phy->ops.write_reg = (hw->mac.type == e1000_82543) 774 if (!(hw->phy.ops.write_reg)) 781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 836 ret_val = hw->phy.ops.write_reg(h [all...] |
H A D | e1000_ich8lan.c | 471 phy->ops.write_reg = e1000_write_phy_reg_hv; 560 phy->ops.write_reg = e1000_write_phy_reg_igp; 569 phy->ops.write_reg = e1000_write_phy_reg_bm; 611 phy->ops.write_reg = e1000_write_phy_reg_bm; 1076 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); 1770 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 2609 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2644 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2656 ret_val = hw->phy.ops.write_reg(h [all...] |
H A D | e1000_i210.c | 763 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); 767 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); 771 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | 779 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); 784 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
|
H A D | e1000_82571.c | 127 phy->ops.write_reg = e1000_write_phy_reg_igp; 140 phy->ops.write_reg = e1000_write_phy_reg_m88; 156 phy->ops.write_reg = e1000_write_phy_reg_bm2; 1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1035 ret_val = phy->ops.write_reg(hw, 1048 ret_val = phy->ops.write_reg(hw,
|
H A D | e1000_api.c | 1001 if (hw->phy.ops.write_reg) 1002 return hw->phy.ops.write_reg(hw, offset, data);
|
H A D | e1000_hw.h | 754 s32 (*write_reg)(struct e1000_hw *, u32, u16); member in struct:e1000_phy_operations
|
/illumos-gate/usr/src/uts/common/io/audio/drv/audiols/ |
H A D | audiols.c | 181 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) function 239 write_reg(dev, SPC, 0x00000f00); 241 write_reg(dev, SPC, 0x0000000f); 253 write_reg(dev, I2C_1, tmp); 258 write_reg(dev, I2C_A, tmp); 287 write_reg(dev, SPI, orig | data); 359 write_reg(dev, SA, tmp); 368 write_reg(dev, SA, tmp); 391 write_reg(dev, SA, tmp); 397 write_reg(de [all...] |
/illumos-gate/usr/src/uts/common/io/e1000g/ |
H A D | e1000g_workarounds.c | 269 hw->phy.ops.write_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value);
|
/illumos-gate/usr/src/uts/common/io/ixgbe/core/ |
H A D | ixgbe_phy.c | 326 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 566 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 828 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 846 hw->phy.ops.write_reg(hw, 864 hw->phy.ops.write_reg(hw, 882 hw->phy.ops.write_reg(hw, 899 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 914 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1098 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1113 hw->phy.ops.write_reg(h [all...] |
H A D | ixgbe_x550.c | 653 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 1346 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1362 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1380 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1397 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1492 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1497 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1679 status = hw->phy.ops.write_reg(hw,
|
H A D | ixgbe_api.c | 554 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
|
H A D | ixgbe_common.c | 358 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
|
H A D | ixgbe_type.h | 3754 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); member in struct:ixgbe_phy_operations
|