/******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
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modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
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this software without specific prior written permission.
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******************************************************************************/
/*$FreeBSD$*/
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
#include "e1000_osdep.h"
#include "e1000_regs.h"
#include "e1000_defines.h"
struct e1000_hw;
#define E1000_REVISION_0 0
#define E1000_FUNC_0 0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
enum e1000_mac_type {
e1000_undefined = 0,
};
enum e1000_media_type {
};
enum e1000_nvm_type {
e1000_nvm_unknown = 0,
};
enum e1000_nvm_override {
};
enum e1000_phy_type {
e1000_phy_unknown = 0,
};
enum e1000_bus_type {
};
enum e1000_bus_speed {
};
enum e1000_bus_width {
};
enum e1000_1000t_rx_status {
};
enum e1000_rev_polarity {
};
enum e1000_fc_mode {
e1000_fc_none = 0,
};
enum e1000_ffe_config {
};
enum e1000_dsp_config {
};
enum e1000_ms_type {
e1000_ms_hw_default = 0,
};
enum e1000_smart_speed {
};
enum e1000_serdes_link_state {
};
/* Receive Descriptor */
struct e1000_rx_desc {
};
/* Receive Descriptor - Extended */
union e1000_rx_desc_extended {
struct {
} read;
struct {
struct {
union {
struct {
} csum_ip;
} hi_dword;
} lower;
struct {
} upper;
};
/* Number of packet split data buffers (not including the header buffer) */
/* Receive Descriptor - Packet Split */
union e1000_rx_desc_packet_split {
struct {
/* one buffer for protocol header(s), three data buffers */
} read;
struct {
struct {
union {
struct {
} csum_ip;
} hi_dword;
} lower;
struct {
} middle;
struct {
/* length of buffers 1-3 */
} upper;
};
/* Transmit Descriptor */
struct e1000_tx_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Offload Context Descriptor */
struct e1000_context_desc {
union {
struct {
} ip_fields;
} lower_setup;
union {
struct {
} tcp_fields;
} upper_setup;
union {
struct {
} fields;
};
/* Offload data descriptor */
struct e1000_data_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
};
struct e1000_vf_stats {
};
struct e1000_phy_stats {
};
struct e1000_host_mng_dhcp_cookie {
};
/* Host Interface "Rev 1" */
struct e1000_host_command_header {
};
struct e1000_host_command_info {
};
/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
};
struct e1000_host_mng_command_info {
};
#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"
#include "e1000_manage.h"
#include "e1000_mbx.h"
/* Function pointers for the MAC. */
struct e1000_mac_operations {
};
/* When to use various PHY register access functions:
*
* Func Caller
* Function Does Does When to use
* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* X_reg L,P,A n/a for simple PHY reg accesses
* X_reg_locked P,A L for multiple accesses of different regs
* on different pages
* X_reg_page A L,P for multiple accesses of different regs
* on the same page
*
* Where X=[read|write], L=locking, P=sets page, A=register access
*
*/
struct e1000_phy_operations {
};
/* Function pointers for the NVM. */
struct e1000_nvm_operations {
};
struct e1000_mac_info {
/* Maximum size of the MTA register table in all supported adapters */
bool adaptive_ifs;
bool has_fwsm;
bool arc_subsystem_valid;
bool asf_firmware_present;
bool autoneg;
bool autoneg_failed;
bool get_link_status;
bool in_ifs_mode;
bool report_tx_early;
bool serdes_has_link;
bool tx_pkt_filtering;
};
struct e1000_phy_info {
bool is_mdix;
bool polarity_correction;
bool speed_downgraded;
bool autoneg_wait_to_complete;
};
struct e1000_nvm_info {
};
struct e1000_bus_info {
};
struct e1000_fc_info {
};
struct e1000_mbx_operations {
};
struct e1000_mbx_stats {
};
struct e1000_mbx_info {
};
struct e1000_dev_spec_82541 {
bool phy_init_script;
bool ttl_workaround;
};
struct e1000_dev_spec_82542 {
bool dma_fairness;
};
struct e1000_dev_spec_82543 {
bool dma_fairness;
bool init_phy_disabled;
};
struct e1000_dev_spec_82571 {
bool laa_is_present;
};
struct e1000_dev_spec_80003es2lan {
bool mdic_wa_enable;
};
struct e1000_shadow_ram {
bool modified;
};
/* I218 PHY Ultra Low Power (ULP) states */
enum e1000_ulp_state {
};
struct e1000_dev_spec_ich8lan {
bool nvm_k1_enabled;
bool disable_k1_off;
bool eee_disable;
bool ulp_capability_disabled;
bool during_suspend_flow;
bool during_dpg_exit;
};
struct e1000_dev_spec_82575 {
bool sgmii_active;
bool global_device_reset;
bool eee_disable;
bool module_plugged;
bool clear_semaphore_once;
bool media_changed;
};
struct e1000_dev_spec_vf {
};
struct e1000_hw {
void *back;
unsigned long io_base;
union {
} dev_spec;
};
#include "e1000_82541.h"
#include "e1000_82543.h"
#include "e1000_82571.h"
#include "e1000_80003es2lan.h"
#include "e1000_ich8lan.h"
#include "e1000_82575.h"
#include "e1000_i210.h"
/* These functions must be implemented by drivers */
#endif