/******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD$*/
/*
* 82575EB Gigabit Network Connection
* 82575EB Gigabit Backplane Connection
* 82575GB Gigabit Network Connection
* 82576 Gigabit Network Connection
* 82576 Quad Port Gigabit Mezzanine Adapter
* 82580 Gigabit Network Connection
* I350 Gigabit Network Connection
*/
#include "e1000_api.h"
#include "e1000_i210.h"
bool active);
bool active);
bool active);
36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
#define E1000_82580_RXPBS_TABLE_SIZE \
(sizeof(e1000_82580_rxpbs_table) / \
sizeof(e1000_82580_rxpbs_table[0]))
/**
* e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
* @hw: pointer to the HW structure
*
* Called to determine if the I2C pins are being used for I2C or as an
* external MDIO interface since the two options are mutually exclusive.
**/
{
DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
case e1000_82575:
case e1000_82576:
break;
case e1000_82580:
case e1000_i350:
case e1000_i354:
case e1000_i210:
case e1000_i211:
break;
default:
break;
}
return ext_mdio;
}
/**
* e1000_init_phy_params_82575 - Init PHY func ptrs.
* @hw: pointer to the HW structure
**/
{
DEBUGFUNC("e1000_init_phy_params_82575");
goto out;
}
if (e1000_sgmii_active_82575(hw)) {
} else {
}
} else {
case e1000_82580:
case e1000_i350:
case e1000_i354:
break;
case e1000_i210:
case e1000_i211:
break;
default:
}
}
/* Set phy->phy_addr and phy->id. */
/* Verify phy id and set remaining function pointers */
case M88E1543_E_PHY_ID:
case M88E1512_E_PHY_ID:
case I347AT4_E_PHY_ID:
case M88E1112_E_PHY_ID:
case M88E1340M_E_PHY_ID:
case M88E1111_I_PHY_ID:
else
/* Check if this PHY is confgured for media swap. */
2);
if (ret_val)
goto out;
&data);
if (ret_val)
goto out;
if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
}
if (ret_val)
goto out;
}
if (ret_val)
goto out;
}
break;
case IGP03E1000_E_PHY_ID:
case IGP04E1000_E_PHY_ID:
break;
case I82580_I_PHY_ID:
case I350_I_PHY_ID:
break;
case I210_I_PHY_ID:
break;
default:
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return ret_val;
}
/**
* e1000_init_nvm_params_82575 - Init NVM func ptrs.
* @hw: pointer to the HW structure
**/
{
DEBUGFUNC("e1000_init_nvm_params_82575");
/*
* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
*/
/* Just in case size is out of range, cap it to the largest
* EEPROM size supported
*/
if (size > 15)
size = 15;
break;
break;
default:
16 : 8;
break;
}
} else {
}
/* Function Pointers */
else
/* override generic family function pointers for specific descendants */
case e1000_82580:
break;
case e1000_i350:
case e1000_i354:
break;
default:
break;
}
return E1000_SUCCESS;
}
/**
* e1000_init_mac_params_82575 - Init MAC func ptrs.
* @hw: pointer to the HW structure
**/
{
DEBUGFUNC("e1000_init_mac_params_82575");
/* Derives media type */
/* Set mta register count */
/* Set uta register count */
/* Set rar entry count */
/* Disable EEE default settings for EEE supported devices */
/* Allow a single clear of the SW semaphore on I210 and newer */
/* Set if part includes ASF firmware */
/* FWSM register */
/* ARC supported; valid only if manageability features are enabled. */
/* Function pointers */
/* reset */
else
/* hw initialization */
else
/* link setup */
/* physical interface link setup */
/* physical interface shutdown */
/* physical interface power up */
/* check for link */
/* read mac address */
/* configure collision distance */
/* multicast address update */
/* writing VFTA */
/* clearing VFTA */
} else {
/* writing VFTA */
/* clearing VFTA */
}
/* ID LED init */
/* blink LED */
/* setup LED */
/* cleanup LED */
/* clear hardware counters */
/* link info */
/* acquire SW_FW sync */
}
/* set lan id for port to determine which phy lock to use */
return E1000_SUCCESS;
}
/**
* e1000_init_function_pointers_82575 - Init func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
**/
{
DEBUGFUNC("e1000_init_function_pointers_82575");
}
/**
* e1000_acquire_phy_82575 - Acquire rights to access PHY
* @hw: pointer to the HW structure
*
* Acquire access rights to the correct PHY.
**/
{
DEBUGFUNC("e1000_acquire_phy_82575");
}
/**
* e1000_release_phy_82575 - Release rights to access PHY
* @hw: pointer to the HW structure
*
* A wrapper to release access rights to the correct PHY.
**/
{
DEBUGFUNC("e1000_release_phy_82575");
}
/**
* e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the PHY register at offset using the serial gigabit media independent
* interface and stores the retrieved information in data.
**/
{
DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
goto out;
}
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write at register offset
*
* Writes the data to PHY register at the offset using the serial gigabit
* media independent interface.
**/
{
DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
goto out;
}
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_get_phy_id_82575 - Retrieve PHY addr and id
* @hw: pointer to the HW structure
*
* Retrieves the PHY address and ID for both PHY's which do and do not use
* sgmi interface.
**/
{
DEBUGFUNC("e1000_get_phy_id_82575");
/* some i354 devices need an extra read for phy id */
/*
* For SGMII PHYs, we try the list of possible addresses until
* we find one that works. For non-SGMII PHYs
* (e.g. integrated copper PHYs), an address of 1 should
* work. The result of this function should mean phy->phy_addr
* and phy->id are set correctly.
*/
if (!e1000_sgmii_active_82575(hw)) {
goto out;
}
if (e1000_sgmii_uses_mdio_82575(hw)) {
case e1000_82575:
case e1000_82576:
break;
case e1000_82580:
case e1000_i350:
case e1000_i354:
case e1000_i210:
case e1000_i211:
break;
default:
ret_val = -E1000_ERR_PHY;
goto out;
break;
}
goto out;
}
/* Power on sgmii phy if it is disabled */
msec_delay(300);
/*
* The address field in the I2CCMD register is 3 bits and 0 is invalid.
* Therefore, we need to test 1-7
*/
if (ret_val == E1000_SUCCESS) {
DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
/*
* At the time of this writing, The M88 part is
* the only supported SGMII PHY product.
*/
if (phy_id == M88_VENDOR)
break;
} else {
DEBUGOUT1("PHY address %u was unreadable\n",
}
}
/* A valid PHY type couldn't be found. */
ret_val = -E1000_ERR_PHY;
} else {
}
/* restore previous sfp cage power state */
out:
return ret_val;
}
/**
* e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
* @hw: pointer to the HW structure
*
* Resets the PHY using the serial gigabit media independent interface.
**/
{
DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
/*
* This isn't a TRUE "hard" reset, but is the only reset
* available to us at this time.
*/
DEBUGOUT("Soft resetting SGMII attached PHY...\n");
goto out;
/*
* SFP documentation requires the following to configure the SPF module
* to work on SGMII. No further documentation is given.
*/
if (ret_val)
goto out;
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure
* @active: TRUE to enable LPLU, FALSE to disable
*
* Sets the LPLU D0 state according to the active flag. When
* activating LPLU this function also disables smart speed
* and vice versa. LPLU will not be activated unless the
* device autonegotiation advertisement meets standards of
* either 10 or 10/100 or 10/100/1000 at all duplexes.
* This is a function pointer entry point only called by
* PHY setup routines.
**/
{
DEBUGFUNC("e1000_set_d0_lplu_state_82575");
goto out;
if (ret_val)
goto out;
if (active) {
data);
if (ret_val)
goto out;
/* When LPLU is enabled, we should disable SmartSpeed */
&data);
data);
if (ret_val)
goto out;
} else {
data);
/*
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
*/
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
}
}
out:
return ret_val;
}
/**
* e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure
* @active: TRUE to enable LPLU, FALSE to disable
*
* Sets the LPLU D0 state according to the active flag. When
* activating LPLU this function also disables smart speed
* and vice versa. LPLU will not be activated unless the
* device autonegotiation advertisement meets standards of
* either 10 or 10/100 or 10/100/1000 at all duplexes.
* This is a function pointer entry point only called by
* PHY setup routines.
**/
{
DEBUGFUNC("e1000_set_d0_lplu_state_82580");
if (active) {
/* When LPLU is enabled, we should disable SmartSpeed */
data &= ~E1000_82580_PM_SPD;
} else {
/*
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
*/
data &= ~E1000_82580_PM_SPD;
}
return E1000_SUCCESS;
}
/**
* e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
* @hw: pointer to the HW structure
*
* Success returns 0, Failure returns 1
*
* The low power link up (lplu) state is set to the power management level D3
* and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
* is used during Dx states where the power conservation is most important.
* During driver activity, SmartSpeed should be enabled so performance is
* maintained.
**/
{
DEBUGFUNC("e1000_set_d3_lplu_state_82580");
if (!active) {
/*
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
*/
data &= ~E1000_82580_PM_SPD;
/* When LPLU is enabled, we should disable SmartSpeed */
data &= ~E1000_82580_PM_SPD;
}
return E1000_SUCCESS;
}
/**
* e1000_acquire_nvm_82575 - Request for access to EEPROM
* @hw: pointer to the HW structure
*
* Acquire the necessary semaphores for exclusive access to the EEPROM.
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
* Return successful if access grant bit set, else clear the request for
* EEPROM access and return -E1000_ERR_NVM (-1).
**/
{
DEBUGFUNC("e1000_acquire_nvm_82575");
if (ret_val)
goto out;
/*
* Check if there is some access
* error this access may hook on
*/
/* Clear all access error flags */
DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
}
}
if (eecd & E1000_EECD_BLOCKED) {
/* Clear access error flag */
DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
}
}
if (ret_val)
out:
return ret_val;
}
/**
* e1000_release_nvm_82575 - Release exclusive access to EEPROM
* @hw: pointer to the HW structure
*
* Stop any current commands to the EEPROM and clear the EEPROM request bit,
* then release the semaphores acquired.
**/
{
DEBUGFUNC("e1000_release_nvm_82575");
}
/**
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're acquiring the lock for.
**/
{
DEBUGFUNC("e1000_acquire_swfw_sync_82575");
while (i < timeout) {
if (e1000_get_hw_semaphore_generic(hw)) {
goto out;
}
break;
/*
* Firmware currently using resource (fwmask)
* or other software thread using resource (swmask)
*/
msec_delay_irq(5);
i++;
}
if (i == timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
goto out;
}
out:
return ret_val;
}
/**
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're releasing the lock for.
**/
{
DEBUGFUNC("e1000_release_swfw_sync_82575");
; /* Empty */
}
/**
* e1000_get_cfg_done_82575 - Read config done bit
* @hw: pointer to the HW structure
*
* Read the management control register for the config done bit for
* completion status. NOTE: silicon which is EEPROM-less will fail trying
* to read the config done bit, so an error is *ONLY* logged and returns
* E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
* would not be able to be reset or change link.
**/
{
DEBUGFUNC("e1000_get_cfg_done_82575");
while (timeout) {
break;
msec_delay(1);
timeout--;
}
if (!timeout)
DEBUGOUT("MNG configuration cycle has not completed.\n");
/* If EEPROM is not marked present, init the PHY manually */
return E1000_SUCCESS;
}
/**
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
*
* This is a wrapper function, if using the serial gigabit media independent
* interface, use PCS to retrieve the link speed and duplex information.
* Otherwise, use the generic function to get the link speed and duplex info.
**/
{
DEBUGFUNC("e1000_get_link_up_info_82575");
duplex);
else
duplex);
return ret_val;
}
/**
* e1000_check_for_link_82575 - Check for link
* @hw: pointer to the HW structure
*
* If sgmii is enabled, then use the pcs register to determine link, otherwise
* use the generic interface for determining link.
**/
{
DEBUGFUNC("e1000_check_for_link_82575");
&duplex);
/*
* Use this flag to determine if link needs to be checked or
* not. If we have link clear the flag so that we do not
* continue to check for link.
*/
/*
* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
*/
if (ret_val)
DEBUGOUT("Error configuring flow control\n");
} else {
}
return ret_val;
}
/**
* e1000_check_for_link_media_swap - Check which M88E1112 interface linked
* @hw: pointer to the HW structure
*
* Poll the M88E1112 interfaces to see which interface achieved link.
*/
{
DEBUGFUNC("e1000_check_for_link_media_swap");
/* Check for copper. */
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
if (data & E1000_M88E1112_STATUS_LINK)
/* Check for other. */
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
if (data & E1000_M88E1112_STATUS_LINK)
/* Determine if a swap needs to happen. */
}
if (port == E1000_MEDIA_PORT_COPPER) {
/* reset page to 0 */
if (ret_val)
return ret_val;
} else {
/* reset page to 0 */
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/**
* e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
* @hw: pointer to the HW structure
**/
{
DEBUGFUNC("e1000_power_up_serdes_link_82575");
return;
/* Enable PCS to turn on link */
/* Power up the laser */
/* flush the write to verify completion */
msec_delay(1);
}
/**
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
*
* Using the physical coding sub-layer (PCS), retrieve the current speed and
* duplex, then store the values in the pointers provided.
**/
{
DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
/*
* Read the PCS Status register for link state. For non-copper mode,
* the status register is not accurate. The PCS status register is
* used instead.
*/
/*
* The link up bit determines when link is up on autoneg.
*/
if (pcs & E1000_PCS_LSTS_LINK_OK) {
/* Detect and store PCS speed */
if (pcs & E1000_PCS_LSTS_SPEED_1000)
*speed = SPEED_1000;
else if (pcs & E1000_PCS_LSTS_SPEED_100)
else
/* Detect and store PCS duplex */
if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
*duplex = FULL_DUPLEX;
else
*duplex = HALF_DUPLEX;
/* Check if it is an I354 2.5Gb backplane connection. */
if ((status & E1000_STATUS_2P5_SKU) &&
!(status & E1000_STATUS_2P5_SKU_OVER)) {
*speed = SPEED_2500;
*duplex = FULL_DUPLEX;
DEBUGOUT("2500 Mbs, ");
DEBUGOUT("Full Duplex\n");
}
}
} else {
*speed = 0;
*duplex = 0;
}
return E1000_SUCCESS;
}
/**
* e1000_shutdown_serdes_link_82575 - Remove link during power down
* @hw: pointer to the HW structure
*
* In the case of serdes shut down sfp and PCS on driver unload
* when management pass thru is not enabled.
**/
{
DEBUGFUNC("e1000_shutdown_serdes_link_82575");
return;
if (!e1000_enable_mng_pass_thru(hw)) {
/* Disable PCS to turn off link */
reg &= ~E1000_PCS_CFG_PCS_EN;
/* shutdown the laser */
/* flush the write to verify completion */
msec_delay(1);
}
return;
}
/**
* e1000_reset_hw_82575 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state.
**/
{
DEBUGFUNC("e1000_reset_hw_82575");
/*
* Prevent the PCI-E bus from sticking if there is no TLP connection
*/
if (ret_val)
DEBUGOUT("PCI-E Master disable polling has failed.\n");
/* set the completion timeout for interface */
if (ret_val)
DEBUGOUT("PCI-E Set completion timeout has failed.\n");
DEBUGOUT("Masking off all interrupts\n");
msec_delay(10);
DEBUGOUT("Issuing a global reset to MAC\n");
if (ret_val) {
/*
* When auto config read does not complete, do not
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
DEBUGOUT("Auto Read Done did not complete\n");
}
/* If EEPROM is not present, run manual init scripts */
/* Clear any pending interrupt events. */
/* Install any alternate MAC address into RAR0 */
return ret_val;
}
/**
* e1000_init_hw_82575 - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation.
**/
{
DEBUGFUNC("e1000_init_hw_82575");
/* Initialize identification LED */
if (ret_val) {
DEBUGOUT("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* Setup the receive address */
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
/* Zero out the Unicast HASH table */
DEBUGOUT("Zeroing the UTA\n");
for (i = 0; i < mac->uta_reg_count; i++)
/* Setup link and flow control */
/* Set the default MTU size */
/*
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
return ret_val;
}
/**
* e1000_setup_copper_link_82575 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Configures the link for auto-neg or forced speed and duplex. Then we check
* for link, once link is established calls to configure collision distance
* and flow control are called.
**/
{
DEBUGFUNC("e1000_setup_copper_link_82575");
ctrl |= E1000_CTRL_SLU;
/* Clear Go Link Disconnect bit on supported devices */
case e1000_82580:
case e1000_i350:
case e1000_i210:
case e1000_i211:
break;
default:
break;
}
if (ret_val)
goto out;
if (e1000_sgmii_active_82575(hw)) {
/* allow time for SFP cage time to power up phy */
msec_delay(300);
if (ret_val) {
DEBUGOUT("Error resetting the PHY.\n");
goto out;
}
}
case e1000_phy_i210:
case e1000_phy_m88:
case I347AT4_E_PHY_ID:
case M88E1112_E_PHY_ID:
case M88E1340M_E_PHY_ID:
case M88E1543_E_PHY_ID:
case M88E1512_E_PHY_ID:
case I210_I_PHY_ID:
break;
default:
break;
}
break;
case e1000_phy_igp_3:
break;
case e1000_phy_82580:
break;
default:
ret_val = -E1000_ERR_PHY;
break;
}
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_setup_serdes_link_82575 - Setup link for serdes
* @hw: pointer to the HW structure
*
* Configure the physical coding sub-layer (PCS) link. The PCS link is
* used on copper connections where the serialized gigabit media independent
* interface (sgmii), or serdes fiber is being used. Configures the link
**/
{
bool pcs_autoneg;
DEBUGFUNC("e1000_setup_serdes_link_82575");
return ret_val;
/*
* On the 82575, SerDes loopback mode persists until it is
* explicitly turned off or a power cycle is performed. A read to
* the register does not indicate its status. Therefore, we ensure
* loopback mode is disabled during initialization.
*/
/* power on the sfp cage if present */
/* set both sw defined pins on 82575/82576*/
/* default pcs_autoneg to the same setting as mac autoneg */
switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
pcs_autoneg = TRUE;
/* autoneg time out should be disabled for SGMII mode */
reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
break;
/* disable PCS autoneg and support parallel detect only */
pcs_autoneg = FALSE;
/* fall through to default case */
default:
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
pcs_autoneg = FALSE;
}
/*
* non-SGMII modes only supports a speed of 1000/Full for the
* link so it is best to just force the MAC and let the pcs
* link either autoneg or be forced to 1000/Full
*/
break;
}
/*
* New SerDes mode allows for forcing speed or autonegotiating speed
* at 1gb. Autoneg should be default set by most drivers. This is the
* mode that will be compatible with older link partners and switches.
*/
if (pcs_autoneg) {
/* Set PCS register for autoneg */
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
/* Disable force flow control for autoneg */
/* Configure flow control advertisement for autoneg */
case e1000_fc_full:
case e1000_fc_rx_pause:
break;
case e1000_fc_tx_pause:
break;
default:
break;
}
} else {
/* Set PCS register for forced link */
/* Force flow control for forced link */
}
return ret_val;
}
/**
* e1000_get_media_type_82575 - derives current media type.
* @hw: pointer to the HW structure
*
* The media type is chosen reflecting few settings.
* The following are taken into account:
* - link mode set in the current port Init Control Word #3
* - current link mode settings in CSR register
* - MDIO vs. I2C PHY control interface chosen
* - SFP module media type
**/
{
/* Set internal phy as default */
/* Get CSR setting */
/* extract link mode setting */
switch (link_mode) {
break;
break;
/* Get phy control interface type set (MDIO vs. I2C)*/
if (e1000_sgmii_uses_mdio_82575(hw)) {
break;
}
/* fall through for I2C based SGMII */
/* read media type from SFP EEPROM */
if ((ret_val != E1000_SUCCESS) ||
/*
* If media type was not identified then return media
* type defined by the CTRL_EXT settings.
*/
if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
}
break;
}
/* do not change link mode for 100BaseFX */
break;
/* change current link mode setting */
else
break;
}
return ret_val;
}
/**
* e1000_set_sfp_media_type_82575 - derives SFP module media type.
* @hw: pointer to the HW structure
*
* The media type is chosen based on SFP module.
* compatibility flags retrieved from SFP ID EEPROM.
**/
{
/* Turn I2C interface ON and power on sfp cage */
/* Read SFP module data */
while (timeout) {
if (ret_val == E1000_SUCCESS)
break;
msec_delay(100);
timeout--;
}
if (ret_val != E1000_SUCCESS)
goto out;
if (ret_val != E1000_SUCCESS)
goto out;
/* Check if there is some SFP module plugged and powered */
if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
} else if (eth_flags->e100_base_fx) {
} else if (eth_flags->e1000_base_t) {
} else {
DEBUGOUT("PHY module has not been recognized\n");
goto out;
}
} else {
}
out:
/* Restore I2C interface setting */
return ret_val;
}
/**
* e1000_valid_led_default_82575 - Verify a valid default LED config
* @hw: pointer to the HW structure
* @data: pointer to the NVM (EEPROM)
*
* Read the EEPROM for the current default LED configuration. If the
* LED configuration is not valid, set to a valid LED configuration.
**/
{
DEBUGFUNC("e1000_valid_led_default_82575");
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
break;
case e1000_media_type_copper:
default:
*data = ID_LED_DEFAULT;
break;
}
}
out:
return ret_val;
}
/**
* e1000_sgmii_active_82575 - Return sgmii state
* @hw: pointer to the HW structure
*
* 82575 silicon has a serialized gigabit media independent interface (sgmii)
* which can be enabled for use in the embedded applications. Simply
* return the current state of the sgmii interface.
**/
{
return dev_spec->sgmii_active;
}
/**
* e1000_reset_init_script_82575 - Inits HW defaults after reset
* @hw: pointer to the HW structure
*
* Inits recommended HW defaults after a reset when there is no EEPROM
* detected. This is only for the 82575.
**/
{
DEBUGFUNC("e1000_reset_init_script_82575");
DEBUGOUT("Running reset init script for 82575\n");
/* SerDes configuration via SERDESCTRL */
/* CCM configuration via CCMCTL register */
/* PCIe lanes configuration */
/* PCIe PLL Configuration */
}
return E1000_SUCCESS;
}
/**
* e1000_read_mac_addr_82575 - Read device MAC address
* @hw: pointer to the HW structure
**/
{
DEBUGFUNC("e1000_read_mac_addr_82575");
/*
* If there's an alternate MAC address place it in RAR0
* so that it will override the Si installed default perm
* address.
*/
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_config_collision_dist_82575 - Configure collision distance
* @hw: pointer to the HW structure
*
* Configures the collision distance to the default value and is used
* during link setup.
**/
{
DEBUGFUNC("e1000_config_collision_dist_82575");
}
/**
* e1000_power_down_phy_copper_82575 - Remove link during PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, remove the link.
**/
{
return;
/* If the management interface is not enabled, then power down */
return;
}
/**
* e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
**/
{
DEBUGFUNC("e1000_clear_hw_cntrs_82575");
/* This register should not be read in copper configurations */
}
/**
* e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
* @hw: pointer to the HW structure
*
* After Rx enable, if manageability is enabled then there is likely some
* bad data at the start of the fifo and possibly in the DMA fifo. This
* function clears the fifos and flushes any packets that came in as rx was
* being enabled.
**/
{
int i, ms_wait;
DEBUGFUNC("e1000_rx_fifo_flush_82575");
/* disable IPv6 options as per hardware errata */
return;
/* Disable all Rx queues */
for (i = 0; i < 4; i++) {
rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
}
/* Poll all queues to verify they have shut down */
msec_delay(1);
rx_enabled = 0;
for (i = 0; i < 4; i++)
if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
break;
}
if (ms_wait == 10)
DEBUGOUT("Queue disable timed out after 10ms\n");
/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
* incoming packets are rejected. Set enable and wait 2ms so that
* any packet that was coming in as RCTL.EN was set is flushed
*/
msec_delay(2);
/* Enable Rx queues that were previously enabled and restore our
* previous state
*/
for (i = 0; i < 4; i++)
/* Flush receive errors generated by workaround */
}
/**
* e1000_set_pcie_completion_timeout - set pci-e completion timeout
* @hw: pointer to the HW structure
*
* The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
* however the hardware default for these parts is 500us to 1ms which is less
* than the 10ms recommended by the pci-e spec. To address this we need to
* increase the value to either 10ms to 200ms for capability version 1 config,
* or 16ms to 55ms for version 2.
**/
{
/* only take action if timeout value is defaulted to 0 */
if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
goto out;
/*
* if capababilities version is type 1 we can write the
* timeout of 10ms to 200ms through the GCR register
*/
if (!(gcr & E1000_GCR_CAP_VER2)) {
goto out;
}
/*
* for version 2 capabilities we need to write the config space
* directly in order to set the completion timeout value for
* 16ms to 55ms
*/
&pcie_devctl2);
if (ret_val)
goto out;
&pcie_devctl2);
out:
/* disable completion timeout resend */
return ret_val;
}
/**
* e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
* @hw: pointer to the hardware struct
* @enable: state to enter, either enabled or disabled
* @pf: Physical Function pool - do not set anti-spoofing for the PF
*
**/
{
case e1000_82576:
break;
case e1000_i350:
case e1000_i354:
break;
default:
return;
}
if (enable) {
/* The PF can spoof - it has to in order to
* support emulation mode NICs
*/
} else {
}
}
/**
* e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
* @hw: pointer to the hardware struct
* @enable: state to enter, either enabled or disabled
*
**/
{
case e1000_82576:
if (enable)
else
break;
case e1000_i350:
case e1000_i354:
if (enable)
else
break;
default:
/* Currently no other hardware supports loopback */
break;
}
}
/**
* e1000_vmdq_set_replication_pf - enable or disable vmdq replication
* @hw: pointer to the hardware struct
* @enable: state to enter, either enabled or disabled
*
**/
{
if (enable)
else
}
/**
* e1000_read_phy_reg_82580 - Read 82580 MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the MDI control register in the PHY at offset and stores the
* information read to data.
**/
{
DEBUGFUNC("e1000_read_phy_reg_82580");
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_write_phy_reg_82580 - Write 82580 MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write to register at offset
*
* Writes data to MDI control register in the PHY at offset.
**/
{
DEBUGFUNC("e1000_write_phy_reg_82580");
if (ret_val)
goto out;
out:
return ret_val;
}
/**
* e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
* @hw: pointer to the HW structure
*
* This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
* the values found in the EEPROM. This addresses an issue in which these
* bits are not restored from EEPROM after reset.
**/
{
DEBUGFUNC("e1000_reset_mdicnfg_82580");
goto out;
if (!e1000_sgmii_active_82575(hw))
goto out;
&nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
if (nvm_data & NVM_WORD24_EXT_MDIO)
if (nvm_data & NVM_WORD24_COM_MDIO)
out:
return ret_val;
}
/**
* e1000_reset_hw_82580 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets function or entire device (all ports, etc.)
* to a known state.
**/
{
/* BH SW mailbox bit in SW_FW_SYNC */
DEBUGFUNC("e1000_reset_hw_82580");
/* 82580 does not reliably do global_device_reset due to hw errata */
/* Get current control state. */
/*
* Prevent the PCI-E bus from sticking if there is no TLP connection
*/
if (ret_val)
DEBUGOUT("PCI-E Master disable polling has failed.\n");
DEBUGOUT("Masking off all interrupts\n");
msec_delay(10);
/* Determine whether or not a global dev reset is requested */
else
ctrl |= E1000_CTRL_RST;
break;
default:
break;
}
/* Add delay to insure DEV_RST or RST has time to complete */
msec_delay(5);
if (ret_val) {
/*
* When auto config read does not complete, do not
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
DEBUGOUT("Auto Read Done did not complete\n");
}
/* clear global device reset status bit */
/* Clear any pending interrupt events. */
if (ret_val)
DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
/* Install any alternate MAC address into RAR0 */
/* Release semaphore */
if (global_device_reset)
return ret_val;
}
/**
* e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
* @data: data received by reading RXPBS register
*
* The 82580 uses a table based approach for packet buffer allocation sizes.
* This function converts the retrieved value into the correct table value
* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
* 0x0 36 72 144 1 2 4 8 16
* 0x8 35 70 140 rsv rsv rsv rsv rsv
*/
{
if (data < E1000_82580_RXPBS_TABLE_SIZE)
return ret_val;
}
/**
* e1000_validate_nvm_checksum_with_offset - Validate EEPROM
* checksum
* @hw: pointer to the HW structure
* @offset: offset in words of the checksum protected region
*
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
**/
{
DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
}
DEBUGOUT("NVM Checksum Invalid\n");
ret_val = -E1000_ERR_NVM;
goto out;
}
out:
return ret_val;
}
/**
* e1000_update_nvm_checksum_with_offset - Update EEPROM
* checksum
* @hw: pointer to the HW structure
* @offset: offset in words of the checksum protected region
*
* up to the checksum. Then calculates the EEPROM checksum and writes the
* value to the EEPROM.
**/
{
DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
if (ret_val) {
DEBUGOUT("NVM Read Error while updating checksum.\n");
goto out;
}
}
&checksum);
if (ret_val)
DEBUGOUT("NVM Write Error while updating checksum.\n");
out:
return ret_val;
}
/**
* e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
* @hw: pointer to the HW structure
*
* the EEPROM and then verifies that the sum of the EEPROM is
* equal to 0xBABA.
**/
{
DEBUGFUNC("e1000_validate_nvm_checksum_82580");
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
/* if chekcsums compatibility bit is set validate checksums
* for all 4 ports. */
eeprom_regions_count = 4;
}
for (j = 0; j < eeprom_regions_count; j++) {
if (ret_val != E1000_SUCCESS)
goto out;
}
out:
return ret_val;
}
/**
* e1000_update_nvm_checksum_82580 - Update EEPROM checksum
* @hw: pointer to the HW structure
*
* each word of the EEPROM up to the checksum. Then calculates the EEPROM
* checksum and writes the value to the EEPROM.
**/
{
DEBUGFUNC("e1000_update_nvm_checksum_82580");
if (ret_val) {
DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
goto out;
}
if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
/* set compatibility bit to validate checksums appropriately */
&nvm_data);
if (ret_val) {
DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
goto out;
}
}
for (j = 0; j < 4; j++) {
if (ret_val)
goto out;
}
out:
return ret_val;
}
/**
* e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
* @hw: pointer to the HW structure
*
* the EEPROM and then verifies that the sum of the EEPROM is
* equal to 0xBABA.
**/
{
u16 j;
DEBUGFUNC("e1000_validate_nvm_checksum_i350");
for (j = 0; j < 4; j++) {
if (ret_val != E1000_SUCCESS)
goto out;
}
out:
return ret_val;
}
/**
* e1000_update_nvm_checksum_i350 - Update EEPROM checksum
* @hw: pointer to the HW structure
*
* each word of the EEPROM up to the checksum. Then calculates the EEPROM
* checksum and writes the value to the EEPROM.
**/
{
u16 j;
DEBUGFUNC("e1000_update_nvm_checksum_i350");
for (j = 0; j < 4; j++) {
if (ret_val != E1000_SUCCESS)
goto out;
}
out:
return ret_val;
}
/**
* @hw: pointer to the HW structure
* @addr: EMI address to program
* @read: boolean flag to indicate read or write
**/
{
DEBUGFUNC("__e1000_access_emi_reg");
if (ret_val)
return ret_val;
if (read)
else
return ret_val;
}
/**
* e1000_read_emi_reg - Read Extended Management Interface register
* @hw: pointer to the HW structure
* @addr: EMI address to program
* @data: value to be read from the EMI address
**/
{
DEBUGFUNC("e1000_read_emi_reg");
}
/**
* e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
* @hw: pointer to the HW structure
*
* Initialize Marvell 1512 to work correctly with Avoton.
**/
{
DEBUGFUNC("e1000_initialize_M88E1512_phy");
/* Check if this is correct PHY. */
goto out;
/* Switch to PHY page 0xFF. */
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Switch to PHY page 0xFB. */
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Switch to PHY page 0x12. */
if (ret_val)
goto out;
/* Change mode to SGMII-to-Copper */
if (ret_val)
goto out;
/* Return the PHY to page 0. */
if (ret_val)
goto out;
if (ret_val) {
DEBUGOUT("Error committing the PHY changes\n");
return ret_val;
}
msec_delay(1000);
out:
return ret_val;
}
/**
* e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
* @hw: pointer to the HW structure
*
* Initialize Marvell 1543 to work correctly with Avoton.
**/
{
DEBUGFUNC("e1000_initialize_M88E1543_phy");
/* Check if this is correct PHY. */
goto out;
/* Switch to PHY page 0xFF. */
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Switch to PHY page 0xFB. */
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Switch to PHY page 0x12. */
if (ret_val)
goto out;
/* Change mode to SGMII-to-Copper */
if (ret_val)
goto out;
/* Switch to PHY page 1. */
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Return the PHY to page 0. */
if (ret_val)
goto out;
if (ret_val) {
DEBUGOUT("Error committing the PHY changes\n");
return ret_val;
}
msec_delay(1000);
out:
return ret_val;
}
/**
* @hw: pointer to the HW structure
* @adv1g: boolean flag enabling 1G EEE advertisement
* @adv100m: boolean flag enabling 100M EEE advertisement
*
*
**/
{
DEBUGFUNC("e1000_set_eee_i350");
goto out;
/* enable or disable per user setting */
if (adv100M)
else
if (adv1G)
else
/* This bit should not be set in normal operation. */
if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
} else {
}
out:
return E1000_SUCCESS;
}
/**
* @hw: pointer to the HW structure
* @adv1g: boolean flag enabling 1G EEE advertisement
* @adv100m: boolean flag enabling 100M EEE advertisement
*
*
**/
{
DEBUGFUNC("e1000_set_eee_i354");
goto out;
/* Switch to PHY page 18. */
if (ret_val)
goto out;
&phy_data);
if (ret_val)
goto out;
phy_data);
if (ret_val)
goto out;
/* Return the PHY to page 0. */
if (ret_val)
goto out;
/* Turn on EEE advertisement. */
&phy_data);
if (ret_val)
goto out;
if (adv100M)
else
if (adv1G)
else
phy_data);
} else {
/* Turn off EEE advertisement. */
&phy_data);
if (ret_val)
goto out;
phy_data);
}
out:
return ret_val;
}
/**
* e1000_get_eee_status_i354 - Get EEE status
* @hw: pointer to the HW structure
* @status: EEE status
*
* Get EEE status by guessing based on whether Tx or Rx LPI indications have
* been received.
**/
{
DEBUGFUNC("e1000_get_eee_status_i354");
/* Check if EEE is supported on this device. */
goto out;
&phy_data);
if (ret_val)
goto out;
out:
return ret_val;
}
/* Due to a hw errata, if the host tries to configure the VFTA register
* while performing queries from the BMC or DMA, then the VFTA in some
* cases won't be written.
*/
/**
* e1000_clear_vfta_i350 - Clear VLAN filter table
* @hw: pointer to the HW structure
*
* Clears the register array which contains the VLAN filter table by
* setting all the values to 0.
**/
{
int i;
DEBUGFUNC("e1000_clear_vfta_350");
for (i = 0; i < 10; i++)
}
}
/**
* e1000_write_vfta_i350 - Write value to VLAN filter table
* @hw: pointer to the HW structure
* @offset: register offset in VLAN filter table
* @value: register value written to VLAN filter table
*
* Writes value at the given offset in the register array which stores
* the VLAN filter table.
**/
{
int i;
DEBUGFUNC("e1000_write_vfta_350");
for (i = 0; i < 10; i++)
}
/**
* e1000_set_i2c_bb - Enable I2C bit-bang
* @hw: pointer to the HW structure
*
* Enable I2C bit-bang interface
*
**/
{
DEBUGFUNC("e1000_set_i2c_bb");
return ret_val;
}
/**
* e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @dev_addr: device address
* @data: value read
*
* Performs byte read operation over I2C interface at
* a specified device address.
**/
{
DEBUGFUNC("e1000_read_i2c_byte_generic");
do {
!= E1000_SUCCESS) {
goto read_byte_out;
}
/* Device Address and write indication */
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
/* Device Address and read indication */
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
break;
fail:
msec_delay(100);
retry++;
DEBUGOUT("I2C byte read error - Retrying.\n");
else
DEBUGOUT("I2C byte read error.\n");
return status;
}
/**
* e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @dev_addr: device address
* @data: value to write
*
* Performs byte write operation over I2C interface at
* a specified device address.
**/
{
DEBUGFUNC("e1000_write_i2c_byte_generic");
goto write_byte_out;
}
do {
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
if (status != E1000_SUCCESS)
goto fail;
break;
fail:
retry++;
DEBUGOUT("I2C byte write error - Retrying.\n");
else
DEBUGOUT("I2C byte write error.\n");
return status;
}
/**
* e1000_i2c_start - Sets I2C start condition
* @hw: pointer to hardware structure
*
* Sets I2C start condition (High -> Low on SDA while SCL is High)
**/
{
DEBUGFUNC("e1000_i2c_start");
/* Start condition must begin with data and clock high */
/* Setup time for start condition (4.7us) */
/* Hold time for start condition (4us) */
/* Minimum low period of clock is 4.7 us */
}
/**
* e1000_i2c_stop - Sets I2C stop condition
* @hw: pointer to hardware structure
*
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
**/
{
DEBUGFUNC("e1000_i2c_stop");
/* Stop condition must begin with data low and clock high */
/* Setup time for stop condition (4us) */
/* bus free time between stop and start (4.7us)*/
}
/**
* e1000_clock_in_i2c_byte - Clocks in one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte to clock in
*
**/
{
s32 i;
bool bit = 0;
DEBUGFUNC("e1000_clock_in_i2c_byte");
*data = 0;
for (i = 7; i >= 0; i--) {
}
return E1000_SUCCESS;
}
/**
* e1000_clock_out_i2c_byte - Clocks out one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte clocked out
*
**/
{
s32 i;
bool bit = 0;
DEBUGFUNC("e1000_clock_out_i2c_byte");
for (i = 7; i >= 0; i--) {
if (status != E1000_SUCCESS)
break;
}
/* Release SDA line (set high) */
return status;
}
/**
* e1000_get_i2c_ack - Polls for I2C ACK
* @hw: pointer to hardware structure
*
**/
{
u32 i = 0;
DEBUGFUNC("e1000_get_i2c_ack");
/* Minimum high period of clock is 4us */
/* Wait until SCL returns high */
for (i = 0; i < timeout; i++) {
usec_delay(1);
if (i2cctl & E1000_I2C_CLK_IN)
break;
}
if (!(i2cctl & E1000_I2C_CLK_IN))
return E1000_ERR_I2C;
if (ack) {
DEBUGOUT("I2C ack was not received.\n");
}
/* Minimum low period of clock is 4.7 us */
return status;
}
/**
* @hw: pointer to hardware structure
* @data: read data value
*
**/
{
DEBUGFUNC("e1000_clock_in_i2c_bit");
/* Minimum high period of clock is 4us */
/* Minimum low period of clock is 4.7 us */
return E1000_SUCCESS;
}
/**
* @hw: pointer to hardware structure
* @data: data value to write
*
**/
{
DEBUGFUNC("e1000_clock_out_i2c_bit");
if (status == E1000_SUCCESS) {
/* Minimum high period of clock is 4us */
/* Minimum low period of clock is 4.7 us.
* This also takes care of the data hold time.
*/
} else {
}
return status;
}
/**
* e1000_raise_i2c_clk - Raises the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Raises the I2C clock line '0'->'1'
**/
{
DEBUGFUNC("e1000_raise_i2c_clk");
*i2cctl |= E1000_I2C_CLK_OUT;
*i2cctl &= ~E1000_I2C_CLK_OE_N;
/* SCL rise time (1000ns) */
}
/**
* e1000_lower_i2c_clk - Lowers the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Lowers the I2C clock line '1'->'0'
**/
{
DEBUGFUNC("e1000_lower_i2c_clk");
*i2cctl &= ~E1000_I2C_CLK_OUT;
*i2cctl &= ~E1000_I2C_CLK_OE_N;
/* SCL fall time (300ns) */
}
/**
* e1000_set_i2c_data - Sets the I2C data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
* @data: I2C data value (0 or 1) to set
*
* Sets the I2C data bit
**/
{
DEBUGFUNC("e1000_set_i2c_data");
if (data)
*i2cctl |= E1000_I2C_DATA_OUT;
else
*i2cctl &= ~E1000_I2C_DATA_OUT;
*i2cctl &= ~E1000_I2C_DATA_OE_N;
*i2cctl |= E1000_I2C_CLK_OE_N;
}
return status;
}
/**
* e1000_get_i2c_data - Reads the I2C SDA data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Returns the I2C data bit value
**/
{
bool data;
DEBUGFUNC("e1000_get_i2c_data");
if (*i2cctl & E1000_I2C_DATA_IN)
data = 1;
else
data = 0;
return data;
}
/**
* e1000_i2c_bus_clear - Clears the I2C bus
* @hw: pointer to hardware structure
*
* Clears the I2C bus by sending nine clock pulses.
* Used when data line is stuck low.
**/
{
u32 i;
DEBUGFUNC("e1000_i2c_bus_clear");
for (i = 0; i < 9; i++) {
/* Min high period of clock is 4us */
/* Min low period of clock is 4.7us*/
}
/* Put the i2c bus back to default state */
}