75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/******************************************************************************
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi Copyright (c) 2001-2015, Intel Corporation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi All rights reserved.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi Redistribution and use in source and binary forms, with or without
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi modification, are permitted provided that the following conditions are met:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 1. Redistributions of source code must retain the above copyright notice,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this list of conditions and the following disclaimer.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 2. Redistributions in binary form must reproduce the above copyright
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi notice, this list of conditions and the following disclaimer in the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi documentation and/or other materials provided with the distribution.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi contributors may be used to endorse or promote products derived from
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this software without specific prior written permission.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi POSSIBILITY OF SUCH DAMAGE.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi******************************************************************************/
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* 82562G 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82562G-2 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82562GT 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82562GT-2 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82562V 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82562V-2 10/100 Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566DC-2 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566DC Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566DM-2 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566DM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566MC Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82566MM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LF Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567V Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LM-2 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LF-2 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567V-2 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LF-3 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LM-3 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82567LM-4 Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82577LM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82577LC Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82578DM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82578DC Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82579LM Gigabit Network Connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 82579V Gigabit Network Connection
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection I217-LM
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection I217-V
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection I218-V
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection I218-LM
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection (2) I218-LM
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection (2) I218-V
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection (3) I218-LM
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Ethernet Connection (3) I218-V
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_on_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_off_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Offset 04h HSFSTS */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 flcdone:1; /* bit 0 Flash Cycle Done */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 flcerr:1; /* bit 1 Flash Cycle Error */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 dael:1; /* bit 2 Direct Access error Log */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 berasesz:2; /* bit 4:3 Sector Erase Size */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 flcinprog:1; /* bit 5 flash cycle in Progress */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Offset 06h FLCTL */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* ICH Flash Region Access Permissions */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 grra:8; /* 0:7 GbE region Read Access */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 grwa:8; /* 8:15 GbE region Write Access */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Test access to the PHY registers by reading the PHY ID registers. If
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the PHY ID is already known (e.g. resume path) compare it with known ID,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * otherwise assume the read PHY ID is correct if it is valid.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Assumes the sw/fw/hw semaphore is already acquired.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (retry_count = 0; retry_count < 2; retry_count++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* In case the PHY needs to be in mdio slow mode,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * set slow mode and try to get the PHY id again.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Only unforce SMBus if ME is not active */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Unforce SMBus mode in PHY */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Unforce SMBus mode in MAC */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * @hw: pointer to the HW structure
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * used to reset the PHY to a quiescent state when necessary.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set Phy Config Counter to 50msec */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Toggle LANPHYPC Value bit */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Workarounds/flow necessary for PHY initialization during driver load
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and resume paths.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Gate automatic PHY configuration by hardware on managed and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * non-managed 82579 and newer adapters.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* It is not possible to be certain of the current state of ULP
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * so forcibly disable it.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Failed to initialize PHY flow\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * inaccessible and resetting the PHY is not blocked, toggle the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * LANPHYPC Value bit to force the interconnect to PCIe mode.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Before toggling LANPHYPC, see if PHY is accessible by
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * forcing MAC to SMBus mode first.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Wait 50 milliseconds for MAC to finish any retries
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * that it might be trying to perform from previous
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * attempts to acknowledge any phy read requests.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-through */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-through */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Toggle LANPHYPC Value bit */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Toggling LANPHYPC brings the PHY out of SMBus mode
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * so ensure that the MAC is also out of SMBus mode
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Check to see if able to reset PHY. Print error if not */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Reset the PHY before any access to it. Doing so, ensures
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * that the PHY is in a known good state before we read/write
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * PHY registers. The generic reset is sufficient here,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * because we haven't determined the PHY type yet.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* On a successful reset, possibly need to wait for the PHY
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * to quiesce to an accessible state before returning control
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * to the calling function. If the PHY does not quiesce, then
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * return E1000E_BLK_PHY_RESET, as this is the condition that
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * the PHY is in.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = hw->phy.ops.check_reset_block(hw);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ERROR_REPORT("ME blocked access to PHY after reset\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Ungate automatic PHY configuration on non-managed 82579 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_phy_params_pchlan - Initialize PHY function pointers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Initialize family-specific PHY parameters and function pointers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.acquire = e1000_acquire_swflag_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.release = e1000_release_swflag_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.reset = e1000_phy_hw_reset_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg = e1000_write_phy_reg_hv;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.power_up = e1000_power_up_phy_copper;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_init_phy_workarounds_pchlan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-through */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* In case the PHY needs to be in mdio slow mode,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * set slow mode and try to get the PHY id again.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->type = e1000_get_phy_type_from_id(phy->id);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_polarity = e1000_check_polarity_82577;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_cable_length = e1000_get_cable_length_82577;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_info = e1000_get_phy_info_82577;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.commit = e1000_phy_sw_reset_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_polarity = e1000_check_polarity_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_cable_length = e1000_get_cable_length_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_info = e1000_get_phy_info_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Initialize family-specific PHY parameters and function pointers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_init_phy_params_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.acquire = e1000_acquire_swflag_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.read_reg = e1000_read_phy_reg_igp;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.release = e1000_release_swflag_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.reset = e1000_phy_hw_reset_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg = e1000_write_phy_reg_igp;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.power_up = e1000_power_up_phy_copper;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* We may need to do this twice - once for IGP and if that fails,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * we'll set BM func pointers and try again
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg = e1000_write_phy_reg_bm;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (i++ < 100)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Verify phy id */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_info = e1000_get_phy_info_igp;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_polarity = e1000_check_polarity_igp;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_info = e1000_get_phy_info_ife;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_polarity = e1000_check_polarity_ife;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.write_reg = e1000_write_phy_reg_bm;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.commit = e1000_phy_sw_reset_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.get_info = e1000_get_phy_info_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.check_polarity = e1000_check_polarity_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Initialize family-specific NVM parameters and function
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 gfpreg, sector_base_addr, sector_end_addr;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_init_nvm_params_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* in SPT, gfpreg doesn't exist. NVM size is taken from the
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * STRAP register. This is because in SPT the GbE Flash region
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * is no longer accessed through the flash registers. Instead,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * the mechanism has changed, and the Flash region access
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * registers are now implemented in GbE memory space.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Adjust to word count */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Set the base address for flash register access */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Can't read flash registers if register set isn't mapped. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("ERROR: Flash registers not mapped\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* sector_X_addr is a "sector"-aligned address (4096 bytes)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Add 1 to sector_end_addr since this sector is included in
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * the overall size.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* flash_base_addr is byte-aligned */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* find total size of the NVM, then cut in half since the total
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * size represents two separate NVM banks.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Adjust to word count */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear shadow ram */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Function Pointers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi nvm->ops.release = e1000_release_nvm_ich8lan;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi nvm->ops.update = e1000_update_nvm_checksum_spt;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Initialize family-specific MAC parameters and function
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_init_mac_params_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set media type function pointer */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.media_type = e1000_media_type_copper;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set mta register count */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set rar entry count */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set if part includes ASF firmware */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* FWSM register */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ARC subsystem not supported */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Adaptive IFS supported */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Function pointers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* function id */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.set_lan_id = e1000_set_lan_id_single_port;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.reset_hw = e1000_reset_hw_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* hw initialization */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* link setup */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.setup_link = e1000_setup_link_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* physical interface setup */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* check for link */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* link info */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* multicast address update */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* clear hardware counters */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* LED and other operations */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* check management mode */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ID LED init */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.id_led_init = e1000_id_led_init_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* blink LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.blink_led = e1000_blink_led_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* setup LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.setup_led = e1000_setup_led_generic;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* cleanup LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* turn on/off LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-through */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* multicast address update for pch2 */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* fall-through */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* check management mode */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ID LED init */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.id_led_init = e1000_id_led_init_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* setup LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.setup_led = e1000_setup_led_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* cleanup LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* turn on/off LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable PCS Lock-loss workaround for ICH8 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * __e1000_access_emi_reg_locked - Read/write EMI register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @addr: EMI address to program
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: pointer to value to read/write from/to the EMI address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @read: boolean flag to indicate read or write
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This helper function assumes the SW/FW/HW Semaphore is already acquired.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("__e1000_access_emi_reg_locked");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_read_emi_reg_locked - Read Extended Management Interface register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @addr: EMI address to program
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: value to be read from the EMI address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Assumes the SW/FW/HW Semaphore is already acquired.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_write_emi_reg_locked - Write Extended Management Interface register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @addr: EMI address to program
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: value to be written to the EMI address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Assumes the SW/FW/HW Semaphore is already acquired.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_eee_pchlan - Enable/disable EEE support
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Enable/disable EEE based on setting in dev_spec structure, the duplex of
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the link and the EEE capabilities of the link partner. The LPI Control
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * register bits will remain set only if/when link is up.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * EEE LPI must not be asserted earlier than one second after link is up.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * On 82579, EEE LPI should not be enabled until such time otherwise there
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * can be link issues with some switches. Other devices can have EEE LPI
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * enabled immediately upon link up since they have a timer in hardware which
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * prevents LPI from being asserted too early.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_set_eee_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear bits that enable EEE in various speeds */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable EEE if not disabled by user */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Save off link partner's EEE ability */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_emi_reg_locked(hw, lpa,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Read EEE advertisement */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable EEE only for speeds in which the link partner is
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * EEE capable and for which we advertise EEE.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* EEE is not supported in 100Half, so ignore
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * partner's EEE in 100 ability if full-duplex
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is not advertised.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @link: link up bool flag
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * preventing further DMA write requests. Workaround the issue by disabling
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the de-assertion of the clock request when in 1Gpbs mode.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * speeds in order to avoid Tx hangs.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi u32 status = E1000_READ_REG(hw, E1000_STATUS);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (link && (status & E1000_STATUS_SPEED_1000)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* clear FEXTNVM6 bit 8 on link down or 10/100 */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Clear link status transmit timeout */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set inband Tx timeout to 5x10us for 100Half */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Do not extend the K1 entry latency for 100Half */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set inband Tx timeout to 50x10us for 10Full/Half */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Extend the K1 entry latency for 10 Mbps */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Determine the latency in nsec based on the LTR value & scale */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_platform_pm_pch_lpt - Set platform power management values
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @link: bool indicating link status
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * when link is up (which must not exceed the maximum latency supported
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * by the platform), otherwise specify there is no LTR requirement.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * latencies in the LTR Extended Capability Structure in the PCIe Extended
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Capability register set, on this device LTR is set by writing the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * message to the PMC.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * high-water mark.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 max_ltr_enc; /* max LTR latency encoded */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Rx Packet Buffer Allocation size (KB) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Determine the maximum latency tolerated by the device.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Per the PCIe spec, the tolerated latencies are encoded as
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * a 3-bit encoded scale (only 0-5 are valid) multiplied by
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * a 10-bit value (0-1023) to provide a range from 1 ns to
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 1=2^5ns, 2=2^10ns,...5=2^25ns.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Determine the maximum latency tolerated by the platform */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set Snoop and No-Snoop latencies the same */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set OBFF high water mark */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable OBFF */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Always unblock interrupts to the CPU even when the system is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in OBFF mode. This ensures that small round-robin traffic
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * (like ping) does not get dropped or experience long latency.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @itr: interrupt throttling rate
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Configure OBFF with the updated interrupt rate.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Convert ITR value into microseconds for OBFF timer */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((timer < 0) || (timer > E1000_ITR_MASK)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Invalid OBFF timer %d\n", timer);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * @hw: pointer to the HW structure
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * @to_sx: boolean indicating a system power state transition to Sx
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * When link is down, configure ULP mode to significantly reduce the power
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * ME firmware to start the ULP configuration. If not on an ME enabled
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * system, configure the ULP mode by software.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Request ME configure ULP mode in the PHY */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Poll up to 5 seconds for Cable Disconnected indication */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Bail if link is re-acquired */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (i++ == 100)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Force SMBus mode in PHY */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Force SMBus mode in MAC */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * LPLU and disable Gig speed when entering ULP
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set Inband ULP Exit, Reset to SMBus mode and
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Disable SMBus Release on PERST# in PHY
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set Disable SMBus Release on PERST# in MAC */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Commit ULP changes in PHY by starting auto ULP configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * @hw: pointer to the HW structure
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * @force: boolean indicating whether or not to force disabling ULP
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Un-configure ULP mode when link is up, the system is transitioned from
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * system, poll for an indication from ME that ULP has been un-configured.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * If not on an ME enabled system, un-configure the ULP mode by software.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * During nominal operation, this function is called when link is acquired
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * to disable ULP mode (force=FALSE); otherwise, for example when unloading
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * the driver or during Sx->S0 transitions, this is called with force=TRUE
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * to forcibly disable ULP.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Request ME un-configure ULP mode in the PHY */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (i++ == 30) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Clear H2ME.ULP after ME ULP configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Toggle LANPHYPC Value bit */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Unforce SMBus mode in PHY */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* The MAC might be in PCIe mode, so temporarily force to
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * SMBus mode in order to access the PHY.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Unforce SMBus mode in MAC */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* When ULP mode was previously entered, K1 was disabled by the
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * hardware. Re-Enable K1 in the PHY when exiting ULP.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Clear ULP enabled configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Commit ULP changes by starting auto ULP configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Clear Disable SMBus Release on PERST# in MAC */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Checks to see of the link status of the hardware has changed. If a
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * change in link status has been detected, then we read the PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * to get the current speed/duplex if link exists.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* We only want to go out to the PHY registers to see if Auto-Neg
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * has completed and/or if our link status has changed. The
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * get_link_status flag is set upon receiving a Link Status
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Change or Rx Sequence Error interrupt.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* First we want to see if the MII Status Register reports
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * link. If so, then we want to get the current speed/duplex
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * of the PHY.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_k1_gig_workaround_hv(hw, link);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* When connected at 10Mbps half-duplex, some parts are excessively
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * aggressive resulting in many collisions. To avoid this, increase
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the IPG and reduce Rx latency in the PHY.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi (hw->mac.type == e1000_pch_spt)) && link) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (duplex == HALF_DUPLEX && speed == SPEED_10) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Reduce Rx latency in analog PHY */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi } else if (hw->mac.type == e1000_pch_spt &&
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi duplex == FULL_DUPLEX && speed != SPEED_1000) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Roll back the default values */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (speed == SPEED_100 || speed == SPEED_10)
ea4c6b78cebe2a3687fa43deeedf6212a124d817Robert Mustacchi hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
ea4c6b78cebe2a3687fa43deeedf6212a124d817Robert Mustacchi hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* I217 Packet Loss issue:
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * ensure that FEXTNVM4 Beacon Duration is set correctly
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * on power up.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Set the Beacon Duration for I217 to 8 usec
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Work-around I218 hang issue */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_k1_workaround_lpt_lp(hw, link);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set platform power management values for
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Latency Tolerance Reporting (LTR)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Optimized Buffer Flush/Fill (OBFF)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_platform_pm_pch_lpt(hw, link);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear link partner's EEE ability */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* FEXTNVM6 K1-off workaround */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
ea4c6b78cebe2a3687fa43deeedf6212a124d817Robert Mustacchi if ((pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) &&
ea4c6b78cebe2a3687fa43deeedf6212a124d817Robert Mustacchi (hw->dev_spec.ich8lan.disable_k1_off == FALSE))
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return E1000_SUCCESS; /* No link detected */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-thru */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_link_stall_workaround_hv(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Workaround for PCHx parts in half-duplex:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Set the number of preambles removed from the packet
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * when it is passed from the PHY to the MAC to prevent
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the MAC from misinterpreting the packet type.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check if there was DownShift, must be checked
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * immediately after link-up
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable/Disable EEE after link up */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If we are forcing speed/duplex, then we simply return since
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * we have already determined whether we have link or not.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Auto-Neg is enabled. Auto Speed Detection takes care
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * of MAC speed/duplex configuration. So we only need to
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * configure Collision Distance in the MAC.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Configure Flow Control now that Auto-Neg has completed.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * First, we need to restore the desired flow control
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * settings because we may have had to re-autoneg with a
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * different link partner.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_config_fc_after_link_up_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Error configuring flow control\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Initialize family-specific function pointers for PHY, MAC, and NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_init_function_pointers_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Acquires the mutex for performing NVM operations.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_release_nvm_ich8lan - Release NVM mutex
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Releases the mutex used while performing NVM operations.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_acquire_swflag_ich8lan - Acquire software control flag
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Acquires the software control flag for performing PHY and select
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * MAC CSR accesses.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("SW has already locked the resource.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_release_swflag_ich8lan - Release software control flag
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Releases the software control flag for performing PHY and select
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * MAC CSR accesses.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_check_mng_mode_ich8lan - Checks management mode
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This checks if the adapter has any manageability enabled.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point only called by read/write
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * routines for the PHY and NVM parts.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_check_mng_mode_pchlan - Checks management mode
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This checks if the adapter has iAMT enabled.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point only called by read/write
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * routines for the PHY and NVM parts.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_rar_set_pch2lan - Set receive address register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @addr: pointer to the receive address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @index: receive address array register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets the receive address array register at index to the address passed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in by addr. For 82579, RAR[0] is the base address register that is to
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Use SHRA[0-3] in place of those reserved for ME.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* HW expects these in little endian so we reverse the byte order
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * from network order (big endian) to little endian
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If MAC address zero, no need to set the AV bit */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* RAR[1-6] are owned by manageability. Skip those and program the
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * next address into the SHRA register array.
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (index < (u32) (hw->mac.rar_entry_count)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_acquire_swflag_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* verify the register updates */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (index - 1), E1000_READ_REG(hw, E1000_FWSM));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Failed to write receive address at index %d\n", index);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_rar_set_pch_lpt - Set receive address registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @addr: pointer to the receive address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @index: receive address array register
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets the receive address register array at index to the address passed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in by addr. For LPT, RAR[0] is the base address register that is to
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * contain the MAC address. SHRA[0-10] are the shared receive address
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * registers that are shared between the Host and manageability engine (ME).
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchistatic int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* HW expects these in little endian so we reverse the byte order
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * from network order (big endian) to little endian
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If MAC address zero, no need to set the AV bit */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* The manageability engine (ME) can lock certain SHRAR registers that
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * it is using - those registers are unavailable for use.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check if all SHRAR registers are locked */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((wlock_mac == 0) || (index <= wlock_mac)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_acquire_swflag_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* verify the register updates */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Failed to write receive address at index %d\n", index);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @mc_addr_list: array of multicast addresses to program
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @mc_addr_count: number of multicast addresses to program
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * The caller must have a packed mc_addr_list of multicast addresses.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < hw->mac.mta_reg_count; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Checks if firmware is blocking the reset of the PHY.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point only called by
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * reset routines.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_check_reset_block_ich8lan");
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Assumes semaphore already acquired.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_write_smbus_addr(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 strap = E1000_READ_REG(hw, E1000_STRAP);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Restore SMBus frequency */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Unsupported SMB frequency in PHY\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * SW should configure the LCD from the NVM extended configuration region
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * as a workaround for certain parts.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u16 word_addr, reg_data, reg_addr, phy_page = 0;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Initialize the PHY from the NVM on ICH platforms. This
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is needed due to an issue where the NVM configuration is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * not properly autoloaded after power transitions.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Therefore, after each PHY reset, we will load the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * configuration data out of the NVM manually.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Fall-thru */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Make sure HW does not configure LCD from PHY
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * extended configuration before SW configuration
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* HW configures the SMBus address and LEDs when the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * OEM and LCD Write Enable bits are set in the NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * When both NVM bits are cleared, SW will configure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * them instead.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Configure LCD from extended configuration region. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* cnf_base_addr is in DWORD */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < cnf_size; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Save off the PHY page for future writes. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_k1_gig_workaround_hv - K1 Si workaround
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @link: link up bool flag
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * from a lower speed. This workaround disables K1 whenever link is at 1Gig
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * If link is down, the function will restore the default K1 setting located
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in the NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Wrap the whole flow with the sw flag */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Link stall fix for link up */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Link stall fix for link down */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_configure_k1_ich8lan - Configure K1 power state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @enable: K1 state to configure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Configure the K1 power state based on the provided parameter.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Assumes semaphore already acquired.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @d0_state: boolean if entering d0 or d3 device state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in NVM determines whether HW should configure LPLU and Gbe Disable.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_oem_bits_config_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set Restart auto-neg to activate the bits */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * done after every PHY reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set MDIO slow mode before any other MDIO access */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable generation of early preamble */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Preamble tuning for SSC */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Return registers to default by doing a soft reset then
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * writing 0x3140 to the control register.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Select page 0 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Configure the K1 Si workaround during phy reset assuming there is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * link so that it disables K1 if link is in 1Gbps.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Workaround for link disconnects on a busy hub in half duplex */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* set MSE higher to enable link to stay up when noise is high */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi for (i = 0; i < (hw->mac.rar_entry_count); i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < 6; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (j = 8; j > 0; j--) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * with 82579 PHY
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @enable: flag to enable/disable workaround when enabling/disabling jumbos
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* disable Rx path while enabling/disabling workaround */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Write Rx addresses (rar_entry_count for RAL/H, and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * SHRAL/H) and initial CRC values to the MAC
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi for (i = 0; i < hw->mac.rar_entry_count; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi addr_high = E1000_READ_REG(hw, E1000_RAH(i));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi addr_low = E1000_READ_REG(hw, E1000_RAL(i));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write Rx addresses to the PHY */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable jumbo frame workaround in the MAC */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable jumbo frame workaround in the PHY */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write MAC register values back to h/w defaults */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write PHY register values back to h/w defaults */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* re-enable Rx path after enabling/disabling workaround */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * done after every PHY reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set MDIO slow mode before any other MDIO access */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* set MSE higher to enable link to stay up when noise is high */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* drop link after 5 times MSE threshold was reached */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_k1_gig_workaround_lv - K1 Si workaround
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * Disable K1 for 1000 and 100 speeds
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set K1 beacon duration based on 10Mbs speed */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* LV 1G/100 Packet drop issue wa */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @gate: boolean set to TRUE to gate, FALSE to ungate
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Gate/ungate the automatic PHY configuration via hardware; perform
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the configuration via software instead.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_lan_init_done_ich8lan - Check for PHY config completion
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Check the appropriate indication the MAC has finished configuring the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PHY after a software reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Wait for basic configuration completes before proceeding */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If basic configuration is incomplete before the above loop
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * count reaches 0, loading the configuration from NVM will
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * leave the PHY in a bad state possibly resulting in no link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear the Init Done bit for the next init event */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Allow time for h/w to get to quiescent state after reset */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Perform any necessary post-reset workarounds */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear the host wakeup bit after lcd reset */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Configure the LCD with the extended configuration region in NVM */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Configure the LCD with the OEM bits in NVM */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Ungate automatic PHY configuration on non-managed 82579 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set EEE LPI Update Timer to 200usec */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Resets the PHY
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point called by drivers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * or other shared routines.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Gate automatic PHY configuration by hardware on non-managed 82579 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @active: TRUE to enable LPLU, FALSE to disable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets the LPLU state according to the active flag. For PCH, if OEM write
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the phy speed. This function will manually set the LPLU bit and restart
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * auto-neg as hw would do. D3 and D0 LPLU will call the same function
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * since it configures the same bit.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @active: TRUE to enable LPLU, FALSE to disable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets the LPLU D0 state according to the active flag. When
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * activating LPLU this function also disables smart speed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and vice versa. LPLU will not be activated unless the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * device autonegotiation advertisement meets standards of
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * either 10 or 10/100 or 10/100/1000 at all duplexes.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point only called by
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PHY setup routines.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Call gig speed drop workaround on LPLU before accessing
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * any PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gig_downshift_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* When LPLU is enabled, we should disable SmartSpeed */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * during Dx states where the power conservation is most
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * important. During driver activity we should enable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * SmartSpeed, so performance is maintained.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (phy->smart_speed == e1000_smart_speed_on) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } else if (phy->smart_speed == e1000_smart_speed_off) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @active: TRUE to enable LPLU, FALSE to disable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets the LPLU D3 state according to the active flag. When
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * activating LPLU this function also disables smart speed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and vice versa. LPLU will not be activated unless the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * device autonegotiation advertisement meets standards of
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * either 10 or 10/100 or 10/100/1000 at all duplexes.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This is a function pointer entry point only called by
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PHY setup routines.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * during Dx states where the power conservation is most
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * important. During driver activity we should enable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * SmartSpeed, so performance is maintained.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (phy->smart_speed == e1000_smart_speed_on) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } else if (phy->smart_speed == e1000_smart_speed_off) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Call gig speed drop workaround on LPLU before accessing
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * any PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gig_downshift_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* When LPLU is enabled, we should disable SmartSpeed */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @bank: pointer to the variable that returns the active bank
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads signature byte from the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* set bank to 0 in case flash read fails */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Check bank 0 */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Check bank 1 */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("ERROR: No valid NVM bank present\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* fall-thru */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* set bank to 0 in case flash read fails */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check bank 0 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check bank 1 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("ERROR: No valid NVM bank present\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * e1000_read_nvm_spt - NVM access for SPT
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @offset: The offset (in bytes) of the word(s) to read.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @words: Size of data to read in words.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @data: pointer to the word(s) to read at offset.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Reads a word(s) from the NVM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("nvm parameter(s) out of bounds\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi act_offset = (bank) ? nvm->flash_bank_size : 0;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (dev_spec->shadow_ram[offset+i].modified) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi data[i] = dev_spec->shadow_ram[offset+i].value;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (!(dev_spec->shadow_ram[offset+i].modified) ||
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi !(dev_spec->shadow_ram[offset+i+1].modified)) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (dev_spec->shadow_ram[offset+i].modified)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi data[i] = dev_spec->shadow_ram[offset+i].value;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (dev_spec->shadow_ram[offset+i].modified)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT1("NVM read error: %d\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_read_nvm_ich8lan - Read word(s) from the NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset (in bytes) of the word(s) to read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @words: Size of data to read in words
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: Pointer to the word(s) to read at offset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads a word(s) from the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("nvm parameter(s) out of bounds\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi act_offset = (bank) ? nvm->flash_bank_size : 0;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < words; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (dev_spec->shadow_ram[offset+i].modified) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi data[i] = dev_spec->shadow_ram[offset+i].value;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_flash_word_ich8lan(hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("NVM read error: %d\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_flash_cycle_init_ich8lan - Initialize flash
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This function does initial flash setup so that a new read/write/erase cycle
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * can be started.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check if the flash descriptor is valid */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear FCERR and DAEL in hw status by writing 1 */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Either we should have a hardware SPI cycle in progress
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * bit to check against, in order to start a new cycle or
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * FDONE bit should be changed in the hardware so that it
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is 1 after hardware reset, which can then be used as an
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * indication whether a cycle is in progress or has been
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* There is no cycle running at present,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * so we can start a cycle.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Begin by setting Flash Cycle Done.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Otherwise poll for sometime so the current
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * cycle has a chance to end before giving up.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Successful in waiting for previous cycle to timeout,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * now set the Flash Cycle Done.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Flash controller busy, cannot get access\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @timeout: maximum time to wait for completion
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This function starts a flash cycle and waits for its completion.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* wait till FDONE bit is set to 1 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } while (i++ < timeout);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * e1000_read_flash_dword_ich8lan - Read dword from flash
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @offset: offset to data location
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @data: pointer to the location for storing the data
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Reads the flash dword at offset into data. Offset is converted
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * to bytes before read.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGFUNC("e1000_read_flash_dword_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Must convert word offset into bytes. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi return e1000_read_flash_data32_ich8lan(hw, offset, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_read_flash_word_ich8lan - Read word from flash
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: offset to data location
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: pointer to the location for storing the data
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads the flash word at offset into data. Offset is converted
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * to bytes before read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_read_flash_word_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Must convert offset into bytes. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_read_flash_byte_ich8lan - Read byte from flash
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset of the byte to read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: Pointer to a byte to store the value read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads a single byte from the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, only 32 bits access is supported,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * so this function should not be called.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_read_flash_data_ich8lan - Read byte or word from NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset (in bytes) of the byte or word to read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @size: Size of data to read, 1=byte 2=word
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: Pointer to the word to store the value read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads a byte or word from the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_read_flash_data_ich8lan");
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_flash_cycle_init_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check if FCERR is set to 1, if set to 1, clear it
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and try the whole sequence a few more times, else
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * read in (shift in) the Flash Data0, the order is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * least significant byte first msb to lsb
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If we've gotten here, then things are probably
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * completely hosed, but if the error condition is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * detected, it won't hurt to give it another try...
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * ICH_FLASH_CYCLE_REPEAT_COUNT times.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Repeat for some time before giving up. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Timeout error - flash cycle did not complete.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * e1000_read_flash_data32_ich8lan - Read dword from NVM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @offset: The offset (in bytes) of the dword to read.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @data: Pointer to the dword to store the value read.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Reads a byte or word from the NVM using the flash access registers.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGFUNC("e1000_read_flash_data_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_flash_cycle_init_ich8lan(hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space, not flash.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Therefore, only 32 bit access is supported
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space, not flash.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * Therefore, only 32 bit access is supported
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Check if FCERR is set to 1, if set to 1, clear it
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * and try the whole sequence a few more times, else
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * read in (shift in) the Flash Data0, the order is
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * least significant byte first msb to lsb
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* If we've gotten here, then things are probably
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * completely hosed, but if the error condition is
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * detected, it won't hurt to give it another try...
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * ICH_FLASH_CYCLE_REPEAT_COUNT times.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Repeat for some time before giving up. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("Timeout error - flash cycle did not complete.\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_write_nvm_ich8lan - Write word(s) to the NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset (in bytes) of the word(s) to write.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @words: Size of data to write in words
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: Pointer to the word(s) to write at offset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Writes a byte or word to the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("nvm parameter(s) out of bounds\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < words; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi dev_spec->shadow_ram[offset+i].modified = TRUE;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi dev_spec->shadow_ram[offset+i].value = data[i];
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * e1000_update_nvm_checksum_spt - Update the checksum for NVM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * The NVM checksum is updated by calling the generic update_nvm_checksum,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * which writes the checksum to the shadow ram. The changes in the shadow
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * ram are then committed to the EEPROM by processing each bank at a time
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * checking for the modified bit and writing only the pending changes.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * After a successful commit, the shadow ram is cleared and is ready for
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * future writes.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGFUNC("e1000_update_nvm_checksum_spt");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_update_nvm_checksum_generic(hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* We're writing to the opposite bank so if we're on bank 1,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * write to bank 0 etc. We also need to erase the segment that
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * is going to be written
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Determine whether to write the value stored
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * in the other NVM bank or a modified value stored
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * in the shadow RAM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_dword_ich8lan(hw,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi dword |= (dev_spec->shadow_ram[i].value & 0xffff);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (dev_spec->shadow_ram[i + 1].modified) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* If the word is 0x13, then make sure the signature bits
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * (15:14) are 11b until the commit has completed.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * This will allow us to write 10b which indicates the
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * signature is valid. We want to do this after the write
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * has completed so that we don't mark the segment valid
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * while the write is still in progress
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Convert offset to bytes. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Write the data to the new bank. Offset in words*/
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Don't bother writing the segment valid bits if sector
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * programming failed.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Finally validate the new segment by setting bit 15:14
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * to 10b in word 0x13 , this can be done without an
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * erase as well since these bits are 11 to start with
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * and we need to change bit 14 to 0b
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /*offset in words but we read dword*/
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* And invalidate the previously valid segment by setting
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * its signature word (0x13) high_byte to 0b. This can be
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * done without an erase because flash erase sets all bits
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * to 1's. We can write 1's to 0's without an erase
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* offset in words but we read dword*/
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Great! Everything worked, we can now clear the cached entries. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Reload the EEPROM, or else modifications will not appear
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * until after the next adapter reset.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT1("NVM update error: %d\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * The NVM checksum is updated by calling the generic update_nvm_checksum,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * which writes the checksum to the shadow ram. The changes in the shadow
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * ram are then committed to the EEPROM by processing each bank at a time
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * checking for the modified bit and writing only the pending changes.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * After a successful commit, the shadow ram is cleared and is ready for
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * future writes.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_update_nvm_checksum_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* We're writing to the opposite bank so if we're on bank 1,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * write to bank 0 etc. We also need to erase the segment that
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is going to be written
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_flash_word_ich8lan(hw, i +
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If the word is 0x13, then make sure the signature bits
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * (15:14) are 11b until the commit has completed.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This will allow us to write 10b which indicates the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * signature is valid. We want to do this after the write
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * has completed so that we don't mark the segment valid
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * while the write is still in progress
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Convert offset to bytes. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write the bytes to the new bank. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Don't bother writing the segment valid bits if sector
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * programming failed.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Finally validate the new segment by setting bit 15:14
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * to 10b in word 0x13 , this can be done without an
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * erase as well since these bits are 11 to start with
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and we need to change bit 14 to 0b
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* And invalidate the previously valid segment by setting
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * its signature word (0x13) high_byte to 0b. This can be
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * done without an erase because flash erase sets all bits
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * to 1's. We can write 1's to 0's without an erase
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Great! Everything worked, we can now clear the cached entries. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Reload the EEPROM, or else modifications will not appear
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * until after the next adapter reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("NVM update error: %d\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * If the bit is 0, that the EEPROM had been modified, but the checksum was not
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * calculated, in which case we need to calculate the checksum and set bit 6.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the checksum needs to be fixed. This bit is an indication that
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the NVM was prepared by OEM software and did not calculate
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the checksum...a likely scenario.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.read(hw, word, 1, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.write(hw, word, 1, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_validate_nvm_checksum_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset (in bytes) of the byte/word to read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @size: Size of data to read, 1=byte 2=word
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: The byte(s) to write to the NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Writes one/two bytes to the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_flash_cycle_init_ich8lan(hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space, not
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * flash. Therefore, only 32 bit access is supported
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * not flash. Therefore, only 32 bit access is
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* check if FCERR is set to 1 , if set to 1, clear it
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and try the whole sequence a few more times else done
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If we're here, then things are most likely
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * completely hosed, but if the error condition
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is detected, it won't hurt to give it another
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Repeat for some time before giving up. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Timeout error - flash cycle did not complete.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @offset: The offset (in bytes) of the dwords to read.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @data: The 4 bytes to write to the NVM.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* Writes one/two/four bytes to the NVM using the flash access registers.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGFUNC("e1000_write_flash_data32_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_flash_cycle_init_ich8lan(hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space, not
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * flash. Therefore, only 32 bit access is supported
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.regval = E1000_READ_FLASH_REG16(hw,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* In SPT, This register is in Lan memory space,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * not flash. Therefore, only 32 bit access is
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* check if FCERR is set to 1 , if set to 1, clear it
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * and try the whole sequence a few more times else done
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* If we're here, then things are most likely
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * completely hosed, but if the error condition
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * is detected, it won't hurt to give it another
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Repeat for some time before giving up. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT("Timeout error - flash cycle did not complete.\n");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The index of the byte to read.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: The byte to write to the NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Writes a single byte to the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_write_flash_byte_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @hw: pointer to the HW structure
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @offset: The offset of the word to write.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* @dword: The dword to write to the NVM.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* Writes a single dword to the NVM using the flash access registers.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi* Goes through a retry algorithm before giving up.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchistatic s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi /* Must convert word offset into bytes. */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi for (program_retries = 0; program_retries < 100; program_retries++) {
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @offset: The offset of the byte to write.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @byte: The byte to write to the NVM.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Writes a single byte to the NVM using the flash access registers.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Goes through a retry algorithm before giving up.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (program_retries = 0; program_retries < 100; program_retries++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @bank: 0 for first bank, 1 for second bank, etc.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * bank N is 4096 * N + flash_reg_addr.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* bank size is in 16bit words - adjust to bytes */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 flash_bank_size = nvm->flash_bank_size * 2;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Determine HW Sector size: Read BERASE bits of hw flash status
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 00: The Hw sector is 256 bytes, hence we need to erase 16
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * consecutive sectors. The start index for the nth Hw sector
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * can be calculated as = bank * 4096 + n * 256
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * The start index for the nth Hw sector can be calculated
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * as = bank * 4096
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * (ich9 only, otherwise error condition)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Hw sector size 256 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Start with the base address, then add the sector offset. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi flash_linear_addr = hw->nvm.flash_base_addr;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi flash_linear_addr += (bank) ? flash_bank_size : 0;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi for (j = 0; j < iteration; j++) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_flash_cycle_init_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write a value 11 (block Erase) in Flash
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Cycle field in hw flash control
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write the last 24 bits of an index within the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * block into Flash Linear address field in Flash
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Check if FCERR is set to 1. If 1,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * clear it and try the whole sequence
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * a few more times else Done
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* repeat for some time before giving up */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_valid_led_default_ich8lan - Set the default LED settings
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @data: Pointer to the LED settings
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reads the LED default settings from the NVM to data. If the NVM LED
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * settings is all 0's or F's, set the LED default to a valid LED default
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_valid_led_default_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_id_led_init_pchlan - store LED configurations
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PCH does not control LEDs via the LEDCTL register, rather it uses
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the PHY LED configuration register.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PCH also does not have an "always on" or "always off" mode which
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * complicates the ID feature. Instead of using the "on" mode to indicate
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * use "link_up" mode. The LEDs will still ID on request if there is no
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * link based on logic in e1000_led_[on|off]_pchlan().
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Get default ID LED modes */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->nvm.ops.valid_led_default(hw, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < 4; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode1 |= (ledctl_off << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Do nothing */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi mac->ledctl_mode2 |= (ledctl_off << shift);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Do nothing */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
ea4c6b78cebe2a3687fa43deeedf6212a124d817Robert Mustacchi * register, so the bus width is hard coded.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_get_bus_info_pcie_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ICH devices are "PCI Express"-ish. They have
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * a configuration space, but do not contain
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * PCI Express Capability registers, so bus width
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * must be hardcoded.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_reset_hw_ich8lan - Reset the hardware
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Does a full reset of the hardware which includes a reset of the PHY and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Prevent the PCI-E bus from sticking if there is no TLP connection
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * on the last TLP read/write transaction when MAC is reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_disable_pcie_master_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("PCI-E Master disable polling has failed.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable the Transmit and Receive units. Then delay to allow
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * any pending transactions to complete before we hit the MAC
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * with the global reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Workaround for ICH8 bit corruption issue in FIFO memory */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set Tx and Rx buffer allocation to 8k apiece. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set Packet Buffer Size to 16k. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Save the NVM K1 bit setting*/
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Full-chip reset requires MAC and PHY reset at the same
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * time to make sure the interface between MAC and the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * external PHY is reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Gate automatic PHY configuration by hardware on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * non-managed 82579
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_acquire_swflag_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Issuing a global reset to ich8lan\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* cannot issue a flush here because it hangs the hardware */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set Phy Config Counter to 50msec */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_post_phy_reset_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* For PCH, this write will make sure that any noise
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * will be detected as a CRC error and be dropped rather than show up
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * as a bad packet to the DMA engine.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_init_hw_ich8lan - Initialize the hardware
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Prepares the hardware for transmit and receive by doing the following:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - initialize hardware bits
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - initialize LED identification
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - setup receive address registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - setup flow control
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - setup transmit descriptors
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * - clear statistics
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Initialize identification LED */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* An error is not fatal and we should not stop init due to this */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Error initializing identification LED\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Setup the receive address. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Zero out the Multicast HASH table */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* The 82578 Rx buffer will stall if wakeup is enabled in host and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the ME. Disable wakeup by clearing the host wakeup bit.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Reset the phy after disabling host wakeup to reset the Rx buffer.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Setup link and flow control */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set the transmit descriptor write-back policy for both queues */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ICH8 has opposite polarity of no_snoop bits.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * By default, we should use snoop behavior.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_set_pcie_no_snoop_generic(hw, snoop);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear all of the statistics registers (clear on read). It is
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * important that we do this after we have tried to establish link
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * because the symbol error count will increment wildly if there
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is no link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Sets/Clears required hardware bits necessary for correctly setting up the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * hardware for transmit and receive.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Extended Device Control */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable PHY low-power state when MAC is at D3 w/o WoL */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Transmit Descriptor Control 0 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Transmit Descriptor Control 1 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Transmit Arbitration Control 0 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Transmit Arbitration Control 1 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Device Status */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* work-around descriptor data corruption issue during nfs v2 udp
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * traffic, just disable the nfs filtering capability
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable IPv6 extension header parsing because some malformed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * IPv6 headers can hang the Rx.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable ECC on Lynxpoint */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_setup_link_ich8lan - Setup flow control and link settings
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Determines which flow control settings to use, then configures flow
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * control. Calls the appropriate media-specific link configuration
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * function. Assuming the adapter has a valid link partner, a valid link
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * should be established. Assumes the hardware has previously been reset
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and the transmitter and receiver are not enabled.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* ICH parts do not have a word in the NVM to determine
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the default flow control setting, so we explicitly
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * set it to full.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (hw->fc.requested_mode == e1000_fc_default)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Save off the requested flow control mode for use later. Depending
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * on the link partner's capabilities, we may or may not use this mode.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->fc.current_mode = hw->fc.requested_mode;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Continue to configure the copper link. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->mac.ops.setup_physical_interface(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_set_fc_watermarks_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Configures the kumeran interface to the PHY to wait the appropriate time
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * when polling the PHY, then call the generic setup_copper_link to finish
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * configuring the copper link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_setup_copper_link_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set the mac to wait the maximum time between each iteration
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and increase the max iterations when polling the phy;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * this fixes erroneous timeouts at 10Mbps.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_copper_link_setup_82577(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_setup_copper_link_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Calls the PHY specific link setup function and then calls the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * generic setup_copper_link to finish configuring the link for
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Lynxpoint PCH devices
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_copper_link_setup_82577(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return e1000_setup_copper_link_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @speed: pointer to store current link speed
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @duplex: pointer to store the current link duplex
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Calls the generic get_speed_and_duplex to retrieve the current link
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * information and then calls the Kumeran lock loss workaround for links at
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * gigabit speeds.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_get_link_up_info_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Work-around for 82566 Kumeran PCS lock loss:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * On link status change (i.e. PCI reset, speed change) and link is up and
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * speed is gigabit-
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 0) if workaround is optionally disabled do nothing
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 1) wait 1ms for Kumeran link to come up
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 2) check Kumeran Diagnostic register PCS lock loss bit
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 3) if not set the link is locked (all is good), otherwise...
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 4) reset the PHY
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 5) repeat up to 10 times
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Note: this is only called for IGP3 copper when speed is 1gb.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!dev_spec->kmrn_lock_loss_workaround_enabled)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Make sure link is up before proceeding. If not just return.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Attempting this while link is negotiating fouled up link
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < 10; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* read once to clear */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* and again to get new status */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* check for PCS lock */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Issue PHY reset */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable GigE link negotiation */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Call gig speed drop workaround on Gig disable before accessing
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * any PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gig_downshift_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* unable to acquire PCS lock */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @state: boolean value used to set the current Kumeran workaround state
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * If ICH8, set the current Kumeran workaround state (enabled - TRUE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * /disabled - FALSE).
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Workaround applies to ICH8 only.\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi dev_spec->kmrn_lock_loss_workaround_enabled = state;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Workaround for 82566 power-down on D3 entry:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 1) disable gigabit link
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 2) write VR power-down enable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 3) read it back
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Continue if successful, else issue LCD reset and repeat
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Try the workaround twice (if needed) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable link */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Call gig speed drop workaround on Gig disable before
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * accessing any PHY registers
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gig_downshift_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Write VR power-down enable */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Read it back and test */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Issue PHY reset and repeat at most one more time */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * LPLU, Gig disable, MDIC PHY reset):
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 1) Set Kumeran Near-end loopback
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 2) Clear Kumeran Near-end loopback
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Should only be called for ICH8[m] devices with any 1G Phy.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * During S0 to Sx transition, it is possible the link remains at gig
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * instead of negotiating to a lower speed. Before going to Sx, set
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 'Gig Disable' to force link speed negotiation to a lower speed based on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * needs to be written.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Parts that support (and are linked to a partner which support) EEE in
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * than 10Mbps w/o EEE.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable LPLU if both link partners support 100BaseT
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * EEE and 100Full is advertised on both ends of the
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * link, and enable Auto Enable LPI since there will
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi * be no driver to enable LPI while in Sx.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Set Auto Enable LPI after link up */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* For i217 Intel Rapid Start Technology support,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * when the system is going into Sx and no manageability engine
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is present, the driver must configure proxy to reset only on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * power good. LPI (Low Power Idle) state must also reset only
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * on power good, as well as the MTA (Multicast table array).
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * The SMBus release must also be disabled on LCD reset.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable proxy to reset only on power good. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Set bit enable LPI (EEE) to reset only on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * power good.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable the SMB release on LCD reset. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable MTA to reset for Intel Rapid Start Technology
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_gig_downshift_workaround_ich8lan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Reset PHY to activate OEM bits on 82577/8 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * During Sx to S0 transitions on non-managed devices or managed devices
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * on which PHY resets are not blocked, if the PHY registers cannot be
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * accessed properly by the s/w toggle the LANPHYPC value to power cycle
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * On i217, setup Intel Rapid Start Technology.
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchiu32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGFUNC("e1000_resume_workarounds_pchlan");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_init_phy_workarounds_pchlan(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* For i217 Intel Rapid Start Technology support when the system
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * is transitioning from Sx and no manageability engine is present
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * configure SMBus to restore on reset, disable proxy, and enable
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * the reset on MTA (Multicast table array).
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi /* Clear Auto Enable LPI after link up */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Restore clear on SMB if no manageability engine
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Disable Proxy */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Enable reset on MTA */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_cleanup_led_ich8lan - Restore the default LED operation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Return the LED back to the default configuration.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_led_on_ich8lan - Turn LEDs on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Turn on the LEDs.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_led_off_ich8lan - Turn LEDs off
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Turn off the LEDs.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_setup_led_pchlan - Configures SW controllable LED
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * This prepares the SW controllable LED for use.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_cleanup_led_pchlan - Restore the default LED operation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Return the LED back to the default configuration.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_led_on_pchlan - Turn LEDs on
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Turn on the LEDs.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_on_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If no link, then turn LED on by setting the invert bit
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * for each LED that's mode is "link_up" in ledctl_mode2.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < 3; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_led_off_pchlan - Turn LEDs off
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Turn off the LEDs.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_led_off_pchlan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If no link, then turn LED off by clearing the invert bit
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * for each LED that's mode is "link_up" in ledctl_mode1.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi for (i = 0; i < 3; i++) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Read appropriate register for the config done bit for completion status
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * and configure the PHY through s/w for EEPROM-less parts.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * NOTE: some silicon which is EEPROM-less will fail trying to read the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * config done bit, so only an error is logged and continues. If we were
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * to return with error, EEPROM-less silicon would not be able to be reset
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * or change link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Wait for indication from h/w that it has completed basic config */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ret_val = e1000_get_auto_rd_done_generic(hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* When auto config read does not complete, do not
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * return with an error. This can happen in situations
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * where there is no eeprom and prevents getting link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("Auto Read Done did not complete\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear PHY Reset Asserted bit */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If EEPROM is not marked present, init the IGP 3 PHY manually */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Maybe we should do a basic PHY config */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * In the case of a PHY power down to save power, or to turn off link during a
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * driver unload, or wake on lan is not enabled, remove the link.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* If the management interface is not enabled, then power down */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * @hw: pointer to the HW structure
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * Clears hardware counters specific to the silicon family and calls
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * clear_hw_cntrs_generic to clear all general purpose counters.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchistatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Clear PHY statistics registers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);