/******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
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******************************************************************************/
/*$FreeBSD$*/
#ifndef _IXGBE_TYPE_H_
#define _IXGBE_TYPE_H_
/*
* The following is a brief description of the error categories used by the
* ERROR_REPORT* macros.
*
* - IXGBE_ERROR_INVALID_STATE
* This category is for errors which represent a serious failure state that is
* unexpected, and could be potentially harmful to device operation. It should
* not be used for errors relating to issues that can be worked around or
* ignored.
*
* - IXGBE_ERROR_POLLING
* used in any case where the timeout occurred, or a failure to obtain a lock, or
* failure to receive data within the time limit.
*
* - IXGBE_ERROR_CAUTION
* This category should be used for reporting issues that may be the cause of
* other errors, such as temperature warnings. It should indicate an event which
* could be serious, but hasn't necessarily caused problems yet.
*
* - IXGBE_ERROR_SOFTWARE
* This category is intended for errors due to software state preventing
* something. The category is not intended for errors due to bad arguments, or
* due to unsupported features. It should be used when a state occurs which
* prevents action but is not a serious issue.
*
* - IXGBE_ERROR_ARGUMENT
* This category is for when a bad or invalid argument is passed. It should be
* used whenever a function is called and error checking has detected the
* argument is wrong or incorrect.
*
* - IXGBE_ERROR_UNSUPPORTED
* This category is for errors which are due to unsupported circumstances or
* configuration issues. It should not be used when the issue is due to an
* invalid argument, but for when something has occurred that is unsupported
* (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
*/
#include "ixgbe_osdep.h"
/* Override this by setting IOMEM in your ixgbe_osdep.h header */
#define IOMEM
/* Vendor ID */
/* Device IDs */
/* General Registers */
/* NVM Registers */
/* General Receive Control */
/* I2CCTL Bit Masks */
#define IXGBE_I2C_DATA_OE_N_EN 0
#define IXGBE_I2C_BB_EN 0
#define IXGBE_I2C_CLK_OE_N_EN 0
/* Interrupt Registers */
/* 82599 EITR is only 12 bits, with the lower 3 always zero */
/*
* 82598 EITR is 16 bits but set the limits based on the max
* supported by all ixgbe hardware
*/
/* Flow Control Registers */
/* Receive DMA Registers */
/*
* Split and Replication Receive Control Registers
* 00-15 : 0x02100 + n*4
* 16-64 : 0x01014 + n*0x40
* 64-127: 0x0D014 + (n-64)*0x40
*/
/*
* Rx DCA Control Register:
* 00-15 : 0x02200 + n*4
* 16-64 : 0x0100C + n*0x40
* 64-127: 0x0D00C + (n-64)*0x40
*/
/* 8 of these 0x03C00 - 0x03C1C */
/* Receive Registers */
#define IXGBE_DRECCCTL_DISABLE 0
/* Multicast Table Array - 128 entries */
/* Packet split receive type */
/* array of 4096 1-bit vlan filters */
/*array of 4096 4-bit vlan vmdq indices */
/* 64 Mailboxes, 16 DW each */
/* Registers for setting up RSS on X550 with SRIOV
* _p - pool number (0..63)
* _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
*/
/* Flow Director registers */
/* Flow Director Stats registers */
/* Flow Director Programming registers */
/* Transmit DMA registers */
/* Anti-spoofing defines */
/* 16 of these (0-15) */
/* Tx DCA Control register : 128 of these (0-127) */
/* Wake up registers */
/* Ext Flexible Host Filter Table */
/* Four Flexible Filters are supported */
/* Six Flexible Filters are supported */
/* Eight Flexible Filters are supported */
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
/* Wake Up Filter Control */
/* Mask for Ext. flex filters */
/* Wake Up Status */
/* Proxy Status */
/* Proxying Filter Control */
/* DCB registers */
/* Power Management */
/* DMA Coalescing configuration */
struct ixgbe_dmac_config {
bool fcoe_en;
};
/*
* DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
* DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
* 87500 bytes [85KB]
*/
/* DMA Coalescing registers */
/* DMA Coalescing register fields */
/* EEE registers */
/* EEE register fields */
/* Security Control Registers */
/* Security Bit Fields and Masks */
/* LinkSec (MacSec) Registers */
/* LinkSec (MacSec) Bit Fields and Masks */
/* IpSec Registers */
/* DCB registers */
#define IXGBE_RTTBCNRC_RF_INT_MASK \
/* BCN (for DCB) Registers */
/* FCoE DMA Context Registers */
/* FCoE Direct DMA Context */
/* FCoE Filter Context Registers */
/* FCoE Direct Filter Context */
/* FCoE Receive Control */
/* FCoE Redirection */
/* Higher 7 bits for the queue index */
/* Stats registers */
/* Management */
/* Management Bit Fields and Masks */
/* Firmware Semaphore Register */
/* ARC Subsystem registers */
/* Driver sets this bit when done to put command in RAM */
/* PCI-E registers */
/* PCI-E registers 82599-Specific */
/* PCI Express Control */
/* Time Sync Registers */
/* Diagnostic Registers */
/* MAC Registers */
/* Statistics Registers */
/* Copper Pond 2 link timeout */
/* Omer CORECTL */
/* BARCTRL */
/* RSCCTL Bit Masks */
/* RSCDBU Bit Masks */
/* RDRXCTL Bit Masks */
/* RQTC Bit Masks and Shifts */
/* PSRTYPE.RQPL Bit masks and shift */
/* CTRL Bit Masks */
/* FACTPS */
/* MHADD Bit Masks */
/* Extended Device Control */
/* Direct Cache Access (DCA) definitions */
/* MSCA Bit Masks */
#define IXGBE_MSCA_NP_ADDR_SHIFT 0
/* MSRWD bit masks */
#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
/* Atlas registers */
/* Atlas bit masks */
/* Omer bit masks */
/* Device Type definitions for new protocol MDIO commands */
/* MII clause 22/28 definitions */
/* PHY IDs*/
/* PHY Types */
/* Special PHY Init Routine */
#define IXGBE_DELAY_NL 0
/* General purpose Interrupt Enable */
/* Packet Buffer Initialization */
/* Packet buffer allocation strategies */
enum {
};
/* Transmit Flow Control status */
/* TCP Timer */
/* HLREG0 Bit Masks */
/* VMD_CTL bitmasks */
/* VT_CTL bitmasks */
/* VMOLR bitmasks */
/* VFRE bitmask */
/* RDHMPN and TDHMPN bitmasks */
/* Receive Checksum Control */
/* FCRTL Bit Masks */
/* PAP bit masks*/
/* RMCS Bit Masks */
/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
/* Deficit Fixed Prio ena */
/* FCCFG Bit Masks */
/* Interrupt register bitmasks */
/* Extended Interrupt Cause Read */
/* Extended Interrupt Cause Set */
/* Extended Interrupt Mask Set */
/* Extended Interrupt Mask Clear */
#define IXGBE_EIMS_ENABLE_MASK ( \
IXGBE_EIMS_LSC | \
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
/* Interrupt clear mask */
/* Interrupt Vector Allocation Registers */
/*
* ETQF filter list: one static filter per filter consumer. This is
* to avoid filter collisions later. Add new filters
* here!!
*
* Current filters:
* EAPOL 802.1x (0x888e): Filter 0
* FCoE (0x8906): Filter 2
* 1588 (0x88f7): Filter 3
* FIP (0x8914): Filter 4
* LLDP (0x88CC): Filter 5
* LACP (0x8809): Filter 6
* FC (0x8808): Filter 7
*/
#define IXGBE_ETQF_FILTER_EAPOL 0
/* VLAN Control Bit Masks */
/* VLAN pool filtering masks */
/* Per VF Port VLAN insertion rules */
/* STATUS Bit Masks */
/* ESDP Bit Masks */
/* LEDCTL Bit Masks */
/* LED modes */
/* AUTOC Bit Masks */
/* Veto Bit definition */
/* LINKS Bit Masks */
/* PCS1GLSTA Bit Masks */
/* PCS1GLCTL Bit Masks */
/* ANLP1 Bit Masks */
/* SW Semaphore Register bitmasks */
/* SW_FW_SYNC/GSSR definitions */
/* FW Status register bitmask */
/* EEC Register */
/* EEPROM Addressing bits based on type (0-small, 1-large) */
/* FLA Register */
/* Part Number String Length */
/* Checksum and EEPROM pointers */
/* MSI-X capability fields masks */
/* Legacy EEPROM word offsets */
/* EEPROM Commands - SPI */
/* EEPROM reset Write Enable latch */
/* EEPROM Read Register */
#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
#endif
/* Number of 5 microseconds we wait for EERD read and
* EERW write to complete */
/* # attempts we wait for flush update to complete */
/* FW header offset */
/* 4KB multiplier */
/* version word 2 (month & day) */
/* version word 3 (silicon compatibility & year) */
/* version word 4 (major & minor numbers) */
/* PCI Bus Info */
/* Number of 100 microseconds we wait for PCI Express master disable */
/* Check whether address is multicast. This is little-endian specific check.*/
/* Check whether an address is broadcast. */
/* RAH */
/* Header split receive */
#define IXGBE_RFCTL_NFS_VER_2 0
/* Transmit Config masks */
/* Enable short packet padding to 64 bytes */
/* This allows for 16K packets + 4k for vlan */
/* Receive Config masks */
/* Receive Priority Flow Control Enable */
/* Multiple Receive Queue Control */
/* Queue Drop Enable */
/* Multiple Transmit Queue Command Register */
/* Receive Descriptor bit definitions */
/* PSRTYPE bit definitions */
/* SRRCTL bit definitions */
* + at bit 8 offset (<< 8)
* = (<< 2)
*/
/* RSS Hash results */
/* RSS Packet Types as indicated in the receive descriptor. */
/* Security Processing bit Indication */
/* Masks to determine if packets should be dropped due to frame errors */
#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
IXGBE_RXD_ERR_CE | \
IXGBE_RXD_ERR_LE | \
IXGBE_RXD_ERR_PE | \
#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
/* Multicast bit mask */
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Vlan-specific macros */
/* SR-IOV specific macros */
/* Translated register #defines */
(0x012300 + (((P) - 24) * 4)))
: (0x0D000 + (0x40 * ((P) - 64))))
: (0x0D004 + (0x40 * ((P) - 64))))
: (0x0D008 + (0x40 * ((P) - 64))))
: (0x0D010 + (0x40 * ((P) - 64))))
: (0x0D018 + (0x40 * ((P) - 64))))
: (0x0D028 + (0x40 * ((P) - 64))))
: (0x0D014 + (0x40 * ((P) - 64))))
: (0x0D00C + (0x40 * ((P) - 64))))
/* Little Endian defines */
#ifndef __le16
#endif
#ifndef __le32
#endif
#ifndef __le64
#endif
#ifndef __be16
/* Big Endian defines */
#endif
enum ixgbe_fdir_pballoc_type {
};
/* Flow Director register values */
#define IXGBE_FDIRFREE_FREE_SHIFT 0
#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
/* Manageablility Host Interface defines */
/* CEM Support */
#define FW_SHADOW_RAM_DUMP_LEN 0
#define FW_INT_PHY_REQ_READ 0
/* Host Interface Command Structures */
struct ixgbe_hic_hdr {
union {
} cmd_or_resp;
};
struct ixgbe_hic_hdr2_req {
};
struct ixgbe_hic_hdr2_rsp {
};
union ixgbe_hic_hdr2 {
};
struct ixgbe_hic_drv_info {
};
/* These need to be dword aligned */
struct ixgbe_hic_read_shadow_ram {
};
struct ixgbe_hic_write_shadow_ram {
};
struct ixgbe_hic_disable_rxen {
};
struct ixgbe_hic_internal_phy_req {
};
struct ixgbe_hic_internal_phy_resp {
};
/* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Transmit Descriptor - Advanced */
union ixgbe_adv_tx_desc {
struct {
} read;
struct {
} wb;
};
/* Receive Descriptor - Legacy */
struct ixgbe_legacy_rx_desc {
};
/* Receive Descriptor - Advanced */
union ixgbe_adv_rx_desc {
struct {
} read;
struct {
struct {
union {
struct {
} hs_rss;
} lo_dword;
union {
struct {
} csum_ip;
} hi_dword;
} lower;
struct {
} upper;
};
/* Context descriptors */
struct ixgbe_adv_tx_context_desc {
};
/* Adv Transmit Descriptor Config Masks */
/* 1st&Last TSO-full iSCSI PDU */
/* Autonegotiation advertised speeds */
/* Link speed */
#define IXGBE_LINK_SPEED_UNKNOWN 0
/* Physical layer type */
#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
/* Flow Control Data Sheet defined values
* Calculation and defines taken from 802.1bb Annex O
*/
/* BitTimes (BT) conversion */
/* Calculate Delay to respond to PFC */
/* Calculate Cable Delay */
/* Calculate Interface Delay X540 */
/* Calculate Interface Delay 82598, 82599 */
/* Calculate Delay incurred from higher layer */
/* Calculate PCI Bus delay for low thresholds */
/* Calculate X540 delay value in bit times */
((36 * \
(IXGBE_B2BT(_max_frame_link) + \
IXGBE_PFC_D + \
(2 * IXGBE_CABLE_DC) + \
(2 * IXGBE_ID_X540) + \
/* Calculate 82599, 82598 delay value in bit times */
((36 * \
(IXGBE_B2BT(_max_frame_link) + \
IXGBE_PFC_D + \
(2 * IXGBE_CABLE_DC) + \
(2 * IXGBE_ID) + \
/* Calculate low threshold delay values */
/* Software ATR hash keys */
/* Software ATR input stream values and masks */
enum ixgbe_atr_flow_type {
};
/* Flow Director ATR input struct. */
union ixgbe_atr_input {
/*
* Byte layout in order, all values with MSB first:
*
* vm_pool - 1 byte
* flow_type - 1 byte
* vlan_id - 2 bytes
* src_ip - 16 bytes
* inner_mac - 6 bytes
* cloud_mode - 2 bytes
* tni_vni - 4 bytes
* dst_ip - 16 bytes
* src_port - 2 bytes
* dst_port - 2 bytes
* flex_bytes - 2 bytes
* bkt_hash - 2 bytes
*/
struct {
} formatted;
};
/* Flow Director compressed ATR hash input struct */
union ixgbe_atr_hash_dword {
struct {
} formatted;
struct {
} port;
};
#define IXGBE_MVALS_INIT(m) \
IXGBE_CAT(SDP0_GPIEN, m), \
IXGBE_CAT(SDP1_GPIEN, m), \
IXGBE_CAT(SDP2_GPIEN, m), \
IXGBE_CAT(EICR_GPI_SDP0, m), \
IXGBE_CAT(EICR_GPI_SDP1, m), \
IXGBE_CAT(EICR_GPI_SDP2, m), \
IXGBE_CAT(I2C_CLK_IN, m), \
IXGBE_CAT(I2C_CLK_OUT, m), \
IXGBE_CAT(I2C_DATA_IN, m), \
IXGBE_CAT(I2C_DATA_OUT, m), \
IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
IXGBE_CAT(I2C_CLK_OE_N_EN, m), \
enum ixgbe_mvals {
};
/*
* Unavailable: The FCoE Boot Option ROM is not present in the flash.
* Disabled: Present; boot order is not set for any targets on the port.
* Enabled: Present; boot order is set for at least one target on the port.
*/
enum ixgbe_fcoe_boot_status {
};
enum ixgbe_eeprom_type {
};
enum ixgbe_mac_type {
ixgbe_mac_unknown = 0,
};
enum ixgbe_phy_type {
ixgbe_phy_unknown = 0,
};
/*
* SFP+ module type IDs:
*
* ID Module Type
* =============
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
* 3 SFP_DA_CU_CORE0 - 82599-specific
* 4 SFP_DA_CU_CORE1 - 82599-specific
*/
enum ixgbe_sfp_type {
ixgbe_sfp_type_da_cu = 0,
};
enum ixgbe_media_type {
};
/* Flow Control Settings */
enum ixgbe_fc_mode {
ixgbe_fc_none = 0,
};
/* Smart Speed Settings */
enum ixgbe_smart_speed {
};
/* PCI bus types */
enum ixgbe_bus_type {
};
/* PCI bus speeds */
enum ixgbe_bus_speed {
};
/* PCI bus widths */
enum ixgbe_bus_width {
};
struct ixgbe_addr_filter_info {
bool user_set_promisc;
};
/* Bus parameters */
struct ixgbe_bus_info {
};
/* Flow control parameters */
struct ixgbe_fc_info {
};
/* Statistics counters collected by the MAC */
struct ixgbe_hw_stats {
};
/* forward declaration */
struct ixgbe_hw;
/* iterator type for walking multicast address lists */
/* Function pointer table */
struct ixgbe_eeprom_operations {
};
struct ixgbe_mac_operations {
/* Link */
bool *);
/* Packet Buffer manipulation */
/* LED */
/* RAR, Multicast, VLAN */
ixgbe_mc_addr_itr, bool clear);
/* Flow Control */
/* Manageability interface */
unsigned int);
};
struct ixgbe_phy_operations {
};
struct ixgbe_eeprom_info {
};
struct ixgbe_mac_info {
/* prefix for World Wide Node Name (WWNN) */
/* prefix for World Wide Port Name (WWPN) */
bool get_link_status;
bool arc_subsystem_valid;
bool autotry_restart;
bool set_lben;
};
struct ixgbe_phy_info {
bool sfp_setup_needed;
bool reset_disable;
bool smart_speed_active;
bool multispeed_fiber;
bool reset_if_overtemp;
bool qsfp_shared_i2c_bus;
};
#include "ixgbe_mbx.h"
struct ixgbe_mbx_operations {
};
struct ixgbe_mbx_stats {
};
struct ixgbe_mbx_info {
};
struct ixgbe_hw {
void *back;
bool adapter_stopped;
int api_version;
bool force_full_reset;
bool allow_unsupported_sfp;
bool wol_enabled;
};
/* Error Codes */
#define IXGBE_SUCCESS 0
#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
#endif /* _IXGBE_TYPE_H_ */