/vbox/src/VBox/VMM/include/ |
H A D | PGMInternal.h | 242 * @param pVCpu The current CPU. 252 # define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \ 253 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS) 255 # define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \ 264 * @param pVCpu The current CPU. 273 # define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \ 274 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS) 276 # define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \ 298 * @param pVCpu The current CPU. 306 #define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhy [all...] |
H A D | SELMInline.h | 101 * @param pVCpu The current virtual CPU. 107 DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl) argument 158 || !CPUMIsGuestInRawMode(pVCpu) ) ) 164 pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu))); 295 * @param pVCpu The current virtual CPU. 299 DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc) argument 307 if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu))
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/vbox/src/VBox/VMM/VMMR3/ |
H A D | TRPM.cpp | 474 PVMCPU pVCpu = &pVM->aCpus[i]; local 476 pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm); 477 pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm); 478 pVCpu->trpm.s.uActiveVector = ~0U; 594 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */ local 595 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT); 618 PVMCPU pVCpu = &pVM->aCpus[0]; 642 RTSEL SelCS = CPUMGetHyperCS(pVCpu); 689 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1); 751 * @param pVCpu Pointe 753 TRPMR3ResetCpu(PVMCPU pVCpu) argument 800 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */ local 882 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */ local 986 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */ local 1048 TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu) argument 1187 PVMCPU pVCpu = &pVM->aCpus[0]; local 1300 PVMCPU pVCpu = &pVM->aCpus[0]; local 1424 PVMCPU pVCpu = &pVM->aCpus[0]; local 1500 TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent) argument [all...] |
H A D | CPUM.cpp | 607 PVMCPU pVCpu = &pVM->aCpus[i]; local 609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum); 610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum); 679 PVMCPU pVCpu = &pVM->aCpus[i]; local 681 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates; 682 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates); 683 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates); 686 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates; 687 pVCpu 761 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 810 PVMCPU pVCpu = &pVM->aCpus[i]; local 834 CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu) argument 1030 PVMCPU pVCpu = &pVM->aCpus[i]; local 1041 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1122 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1158 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1187 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1233 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1383 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1749 PVMCPU pVCpu = VMMGetCpu(pVM); local 1772 PVMCPU pVCpu = VMMGetCpu(pVM); local 1795 PVMCPU pVCpu = &pVM->aCpus[0]; local 1908 PVMCPU pVCpu; member in struct:CPUMDISASSTATE 2017 CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix) argument 2131 CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl) argument 2166 CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels) argument 2190 PVMCPU pVCpu = &pVM->aCpus[i]; local [all...] |
H A D | DBGFDisas.cpp | 60 PVMCPU pVCpu; member in struct:__anon16844 102 * @param pVCpu Pointer to the VMCPU. 109 static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode, argument 122 pState->pVCpu = pVCpu; 251 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock); 404 * @param pVCpu Pointer to the VMCPU. 416 dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags, argument 419 VMCPU_ASSERT_EMT(pVCpu); 430 pCtxCore = CPUMGetGuestCtxCore(pVCpu); 712 PVMCPU pVCpu = VMMGetCpu(pVM); local 734 DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput) argument 757 DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix) argument 790 DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix) argument [all...] |
H A D | CPUMDbg.cpp | 41 PVMCPU pVCpu = (PVMCPU)pvUser; local 42 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 44 VMCPU_ASSERT_EMT(pVCpu); 64 PVMCPU pVCpu = (PVMCPU)pvUser; local 65 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister; 67 VMCPU_ASSERT_EMT(pVCpu); 110 PVMCPU pVCpu = (PVMCPU)pvUser; local 111 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister; 113 VMCPU_ASSERT_EMT(pVCpu); 133 PVMCPU pVCpu local 191 PVMCPU pVCpu = (PVMCPU)pvUser; local 218 PVMCPU pVCpu = (PVMCPU)pvUser; local 279 PVMCPU pVCpu = (PVMCPU)pvUser; local 356 PVMCPU pVCpu = (PVMCPU)pvUser; local 379 PVMCPU pVCpu = (PVMCPU)pvUser; local 436 PVMCPU pVCpu = (PVMCPU)pvUser; local 459 PVMCPU pVCpu = (PVMCPU)pvUser; local 506 PVMCPU pVCpu = (PVMCPU)pvUser; local 535 PVMCPU pVCpu = (PVMCPU)pvUser; local 594 PVMCPU pVCpu = (PVMCPU)pvUser; local 630 PVMCPU pVCpu = (PVMCPU)pvUser; local 671 PVMCPU pVCpu = (PVMCPU)pvUser; local [all...] |
H A D | DBGFAddr.cpp | 237 * @param pVCpu Pointer to the VMCPU. 241 static DECLCALLBACK(int) dbgfR3AddrToPhysOnVCpu(PVMCPU pVCpu, PDBGFADDRESS pAddress, PRTGCPHYS pGCPhys) argument 243 VMCPU_ASSERT_EMT(pVCpu); 245 return PGMGstGetPage(pVCpu, pAddress->FlatPtr, NULL, pGCPhys); 296 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local 297 if (VMCPU_IS_EMT(pVCpu)) 298 rc = dbgfR3AddrToPhysOnVCpu(pVCpu, pAddress, pGCPhys); 300 rc = VMR3ReqPriorityCallWaitU(pUVM, pVCpu->idCpu, 301 (PFNRT)dbgfR3AddrToPhysOnVCpu, 3, pVCpu, pAddress, pGCPhys); 409 PVMCPU pVCpu local [all...] |
H A D | DBGFMem.cpp | 72 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local 73 PGMMODE enmMode = PGMGetGuestMode(pVCpu); 97 rc = PGMR3DbgScanVirtual(pVM, pVCpu, pAddress->FlatPtr, cbRange, *puAlign, pabNeedle, cbNeedle, &GCPtrHit); 177 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local 178 PGMMODE enmMode = PGMGetGuestMode(pVCpu); 192 rc = PGMPhysSimpleReadGCPtr(pVCpu, pvBuf, pAddress->FlatPtr, cbRead); 341 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local 342 PGMMODE enmMode = PGMGetGuestMode(pVCpu); 356 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pAddress->FlatPtr, pvBuf, cbWrite); 396 PVMCPU pVCpu local 594 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local [all...] |
H A D | PATMGuest.cpp | 94 PVMCPU pVCpu = VMMGetCpu0(pVM); local 103 rc = PGMPhysSimpleReadGCPtr(pVCpu, uTemp, lpfnKiFastSystemCall, sizeof(uFnKiFastSystemCall)); 113 rc = PGMPhysSimpleReadGCPtr(pVCpu, uTemp, pInstrGC + i, sizeof(uFnKiIntSystemCall)); 138 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aPrivInstr, pPatch->pPrivInstrGC, SIZEOF_NEARJUMP32); 144 rc = PGMPhysSimpleDirtyWriteGCPtr(pVCpu, pInstrGC, uTemp, SIZEOF_NEARJUMP32);
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H A D | SELM.cpp | 253 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */ local 254 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS); 255 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT); 256 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT); 438 PVMCPU pVCpu = &pVM->aCpus[i]; local 443 CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1); 446 CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]); 447 CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]); 448 CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]); 449 CPUMSetHyperSS(pVCpu, pV 461 PVMCPU pVCpu = &pVM->aCpus[0]; local 624 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */ local 738 PVMCPU pVCpu = VMMGetCpu(pVM); local 780 selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu) argument 1043 selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu) argument 1278 selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu) argument 1381 SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu) argument 1538 SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu) argument 1777 PVMCPU pVCpu = VMMGetCpu(pVM); local 1915 PVMCPU pVCpu = VMMGetCpu(pVM); local 2102 selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2263 selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2370 SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2597 PVMCPU pVCpu = &pVM->aCpus[0]; local 2665 PVMCPU pVCpu = &pVM->aCpus[0]; local [all...] |
H A D | DBGF.cpp | 227 PVMCPU pVCpu = VMMGetCpu(pVM); local 246 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST)) 251 rc = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, true /*fPriorityOnly*/); 359 PVMCPU pVCpu = VMMGetCpu(pVM); local 410 PVMCPU pVCpu = &pVM->aCpus[0]; local 412 switch (EMGetState(pVCpu)) 443 PVMCPU pVCpu = VMMGetCpu(pVM); local 461 REMR3StateUpdate(pVM, pVCpu); 624 PVMCPU pVCpu = VMMGetCpu0(pVM); 627 RTUINT iBp = pVM->dbgf.s.DbgEvent.u.Bp.iBp = pVCpu 663 PVMCPU pVCpu = VMMGetCpu(pVM); local 816 PVMCPU pVCpu = VMMGetCpu0(pVM); local 858 PVMCPU pVCpu = VMMGetCpu0(pVM); local 1206 DBGFR3PrgStep(PVMCPU pVCpu) argument [all...] |
H A D | PDMDevMiscHlp.cpp | 64 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local 67 pDevIns->pReg->szName, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))); 69 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC); 71 REMR3NotifyInterruptSet(pVM, pVCpu); 73 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_DONE_REM | VMNOTIFYFF_FLAGS_POKE); 82 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local 95 pDevIns->pReg->szName, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))); 97 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC); 99 REMR3NotifyInterruptClear(pVM, pVCpu); 186 PVMCPU pVCpu local 223 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local [all...] |
H A D | IOM.cpp | 252 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 253 pVCpu->iom.s.pRangeLastReadR0 = NIL_RTR0PTR; 254 pVCpu->iom.s.pRangeLastWriteR0 = NIL_RTR0PTR; 255 pVCpu->iom.s.pStatsLastReadR0 = NIL_RTR0PTR; 256 pVCpu->iom.s.pStatsLastWriteR0 = NIL_RTR0PTR; 257 pVCpu->iom.s.pMMIORangeLastR0 = NIL_RTR0PTR; 258 pVCpu->iom.s.pMMIOStatsLastR0 = NIL_RTR0PTR; 260 pVCpu->iom.s.pRangeLastReadR3 = NULL; 261 pVCpu->iom.s.pRangeLastWriteR3 = NULL; 262 pVCpu 320 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local 1496 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); local 1555 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); local 1606 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); local [all...] |
H A D | CSAM.cpp | 356 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VPCU */ local 357 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION); 699 PVMCPU pVCpu = VMMGetCpu0(pVM); local 724 rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, pGCPtr, (const void **)&pHCPtr, &pCacheRec->Lock); 1281 PVMCPU pVCpu = VMMGetCpu0(pVM); local 1367 if (!PGMGstIsPagePresent(pVCpu, pCurInstrGC + cbInstr - 1)) 1411 PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu.Param1.uDisp.i32, sizeof(addr)); 1430 if (!PGMGstIsPagePresent(pVCpu, addr)) 1484 rc2 = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, pJumpTableGC, (PRTHCPTR)&pJumpTableHC, missing page lock); 1498 rc2 = PGMGstGetPage(pVCpu, add 1560 PVMCPU pVCpu = VMMGetCpu0(pVM); local 1633 PVMCPU pVCpu = VMMGetCpu0(pVM); local 1824 PVMCPU pVCpu = VMMGetCpu0(pVM); local 1927 PVMCPU pVCpu = VMMGetCpu0(pVM); local 2076 PVMCPU pVCpu = VMMGetCpu0(pVM); local 2403 PVMCPU pVCpu = VMMGetCpu0(pVM); local 2456 PVMCPU pVCpu = VMMGetCpu0(pVM); local 2480 CSAMR3DoPendingAction(PVM pVM, PVMCPU pVCpu) argument 2503 PVMCPU pVCpu = VMMGetCpu0(pVM); local [all...] |
/vbox/src/VBox/VMM/VMMAll/ |
H A D | IOMAll.cpp | 223 * @param pVCpu Pointer to the virtual CPU structure of the caller. 228 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue) argument 247 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastRead); 252 pVCpu->iom.s.CTX_SUFF(pStatsLastRead) = pStats; 259 CTX_SUFF(PIOMIOPORTRANGE) pRange = pVCpu->iom.s.CTX_SUFF(pRangeLastRead); 265 pVCpu->iom.s.CTX_SUFF(pRangeLastRead) = pRange; 385 * @param pVCpu Pointer to the virtual CPU structure of the caller. 391 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, argument 412 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastRead); 417 pVCpu 532 IOMIOPortWrite(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue) argument 670 IOMIOPortWriteString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb) argument 813 PVMCPU pVCpu = VMMGetCpu(pVM); local 912 IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument 973 IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument [all...] |
H A D | PGMAllPhys.cpp | 90 PVMCPU pVCpu = VMMGetCpu(pVM); local 106 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState; 107 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp); 118 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestROMWriteHandled); 142 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestROMWriteUnhandled); 332 * @param pVCpu Pointer to the VMCPU. 334 VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu) argument 336 LogFlow(("PGMPhysIsA20Enabled %d\n", pVCpu->pgm.s.fA20Enabled)); 337 return pVCpu->pgm.s.fA20Enabled; 1472 PVMCPU pVCpu local 1524 PVMCPU pVCpu = VMMGetCpu(pVM); local 1599 PVMCPU pVCpu = VMMGetCpu(pVM); local 1700 PVMCPU pVCpu = VMMGetCpu(pVM); local 1773 PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock) argument 1807 PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock) argument 2005 PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys) argument 2024 PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys) argument 3010 PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb) argument 3101 PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb) argument 3181 PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb) argument 3262 PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb) argument 3350 PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb) argument 3454 PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb) argument 3636 PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap) argument 3829 PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, bool fRaiseTrap) argument 4055 PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock) argument [all...] |
H A D | TMAll.cpp | 118 * @param pVCpu Pointer to the VMCPU. 120 VMMDECL(void) TMNotifyStartOfExecution(PVMCPU pVCpu) argument 122 PVM pVM = pVCpu->CTX_SUFF(pVM); 125 pVCpu->tm.s.u64NsTsStartExecuting = RTTimeNanoTS(); 128 tmCpuTickResume(pVM, pVCpu); 140 * @param pVCpu Pointer to the VMCPU. 142 VMMDECL(void) TMNotifyEndOfExecution(PVMCPU pVCpu) argument 144 PVM pVM = pVCpu->CTX_SUFF(pVM); 147 tmCpuTickPause(pVCpu); 151 uint64_t const cNsTotalNew = u64NsTs - pVCpu 190 TMNotifyStartOfHalt(PVMCPU pVCpu) argument 214 TMNotifyEndOfHalt(PVMCPU pVCpu) argument 745 tmTimerPollReturnHit(PVM pVM, PVMCPU pVCpu, PVMCPU pVCpuDst, uint64_t u64Now, uint64_t *pu64Delta, PSTAMCOUNTER pCounter) argument 771 tmTimerPollInternal(PVM pVM, PVMCPU pVCpu, uint64_t *pu64Delta) argument 982 TMTimerPollBool(PVM pVM, PVMCPU pVCpu) argument 1000 TMTimerPollVoid(PVM pVM, PVMCPU pVCpu) argument 1019 TMTimerPollGIP(PVM pVM, PVMCPU pVCpu, uint64_t *pu64Delta) argument 2531 TMCalcHostTimerFrequency(PVM pVM, PVMCPU pVCpu) argument [all...] |
H A D | PDMAllCritSectRw.cpp | 85 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu); 86 RTNATIVETHREAD hNativeSelf = pVCpu->hNativeThread; Assert(hNativeSelf != NIL_RTNATIVETHREAD); 134 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu); local 135 int rc = VMMRZCallRing3(pVM, pVCpu, VMMCALLRING3_VM_R0_PREEMPT, NULL); 374 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu); 377 return VMMRZCallRing3(pVM, pVCpu, VMMCALLRING3_PDM_CRIT_SECT_RW_ENTER_SHARED, MMHyperCCToR3(pVM, pThis)); 624 PVMCPU pVCpu [all...] |
H A D | DBGFAll.cpp | 172 * @param pVCpu The cross context CPU structure for the calling EMT. 177 VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue) argument 199 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp; 200 pVCpu->dbgf.s.fSingleSteppingRaw = false; 261 * @param pVCpu Pointer to the VMCPU. 263 VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu) argument 265 return pVCpu->dbgf.s.fSingleSteppingRaw;
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/vbox/src/VBox/Debugger/testcase/ |
H A D | tstDBGCStubs.cpp | 331 VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu) argument 336 VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu) argument 341 VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu) argument 346 VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu) argument 351 VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu) argument 356 VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu) argument 361 VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit) argument 366 VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu) argument 371 VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu) argument 376 VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu) argument 381 CPUMQueryGuestCtxPtr(PVMCPU pVCpu) argument 386 CPUMIsGuestIn64BitCode(PVMCPU pVCpu) argument 391 CPUMGetGuestEFlags(PVMCPU pVCpu) argument 405 PGMGetHyperCR3(PVMCPU pVCpu) argument 410 PGMGetShadowMode(PVMCPU pVCpu) argument [all...] |
/vbox/src/recompiler/ |
H A D | VBoxRecompiler.c | 101 static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu); 323 PVMCPU pVCpu = VMMGetCpu(pVM); local 324 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features); 325 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features); 737 PVMCPU pVCpu = VMMGetCpu(pVM); local 738 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features); 739 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features); 751 PVMCPU pVCpu = &pVM->aCpus[i]; local 752 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL); 773 * @param pVCpu VMCP 775 REMR3Step(PVM pVM, PVMCPU pVCpu) argument 902 REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu) argument 1055 remR3RunLoggingStep(PVM pVM, PVMCPU pVCpu) argument 1258 REMR3Run(PVM pVM, PVMCPU pVCpu) argument 2089 REMR3State(PVM pVM, PVMCPU pVCpu) argument 2531 REMR3StateBack(PVM pVM, PVMCPU pVCpu) argument 2806 remR3StateUpdate(PVM pVM, PVMCPU pVCpu) argument 2992 REMR3StateUpdate(PVM pVM, PVMCPU pVCpu) argument 3015 REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable) argument 3163 REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage) argument 4055 PVMCPU pVCpu = VMMGetCpu(pVM); local 4129 PVMCPU pVCpu = cpu_single_env->pVCpu; local 4221 REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt) argument 4247 REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu) argument 4268 REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu) argument 4758 PVMCPU pVCpu; local 4821 PVMCPU pVCpu; local 4848 remR3DumpLnxSyscall(PVMCPU pVCpu) argument 5148 remR3DumpOBsdSyscall(PVMCPU pVCpu) argument [all...] |
/vbox/src/VBox/VMM/VMMR0/ |
H A D | PGMR0SharedPage.cpp | 51 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local 75 rc = PGMGstGetPage(pVCpu, GCPtrPage, &fFlags, &GCPhys); 110 || ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3) 111 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)));
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H A D | PDMR0Device.cpp | 439 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local 442 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))); 444 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC); 464 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local 467 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))); 469 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC); 516 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local 521 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu)); 526 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC); 529 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NM 567 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local [all...] |
/vbox/src/VBox/VMM/VMMRC/ |
H A D | CSAMRC.cpp | 69 PVMCPU pVCpu = VMMGetCpu0(pVM); local 93 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT); 122 VMCPU_FF_SET(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION); 134 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
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/vbox/src/VBox/VMM/VMMRZ/ |
H A D | PGMRZDynMap.cpp | 1346 * @param pVCpu The current CPU, for statistics. 1350 static uint32_t pgmR0DynMapPageSlow(PPGMRZDYNMAP pThis, RTHCPHYS HCPhys, uint32_t iPage, PVMCPU pVCpu, bool *pfNew) argument 1352 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlow); 1380 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlowLoopHits); 1392 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlowLoopMisses); 1404 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZDynMapPageSlowLostHits); 1453 * @param pVCpu The current CPU (for statistics). 1456 DECLINLINE(uint32_t) pgmR0DynMapPage(PPGMRZDYNMAP pThis, RTHCPHYS HCPhys, int32_t iRealCpu, PVMCPU pVCpu, void **ppvPage) argument 1460 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPage); 1475 STAM_COUNTER_INC(&pVCpu 1831 PGMRZDynMapStartAutoSet(PVMCPU pVCpu) argument 1854 PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu) argument 1930 PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu) argument 1963 PGMRZDynMapFlushAutoSet(PVMCPU pVCpu) argument 2006 PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu) argument 2102 PGMRZDynMapPushAutoSubset(PVMCPU pVCpu) argument 2134 PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset) argument 2165 pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL) argument 2284 PVMCPU pVCpu = PGMRZDYNMAP_SET_2_VMCPU(pSet); local [all...] |