Lines Matching refs:pVCpu
607 PVMCPU pVCpu = &pVM->aCpus[i];
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
679 PVMCPU pVCpu = &pVM->aCpus[i];
681 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
682 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
683 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
686 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
687 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
688 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
691 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
692 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
693 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
696 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
761 PVMCPU pVCpu = &pVM->aCpus[iCpu];
762 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
763 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
764 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
767 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
810 PVMCPU pVCpu = &pVM->aCpus[i];
811 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
813 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
814 pVCpu->cpum.s.uMagic = 0;
830 * @param pVCpu Pointer to the cross context virtual CPU structure of
834 VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
837 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
842 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
848 pVCpu->cpum.s.fUseFlags = fUseFlags;
942 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
948 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
958 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
963 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
970 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1030 PVMCPU pVCpu = &pVM->aCpus[i];
1031 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Hyper.pXStateR3),
1033 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1041 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1043 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Guest.pXStateR3),
1045 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1047 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1048 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1049 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1050 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1122 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1123 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1124 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1126 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(pVCpu->cpum.s.Hyper.pXStateR3->x87),
1128 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1130 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1131 pVCpu->cpum.s.Hyper.rsp = uRSP;
1158 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1159 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(pVCpu->cpum.s.Guest.pXStateR3->x87),
1161 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1163 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1164 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1166 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1169 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1175 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1176 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
1177 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1178 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
1187 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1190 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1191 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1200 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1201 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1214 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1215 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1217 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1218 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1233 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1234 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1235 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1236 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1237 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1238 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1239 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1383 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1386 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1389 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
1393 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1749 PVMCPU pVCpu = VMMGetCpu(pVM);
1750 if (!pVCpu)
1751 pVCpu = &pVM->aCpus[0];
1753 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1755 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1772 PVMCPU pVCpu = VMMGetCpu(pVM);
1773 if (!pVCpu)
1774 pVCpu = &pVM->aCpus[0];
1778 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1795 PVMCPU pVCpu = &pVM->aCpus[0];
1799 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
1908 PVMCPU pVCpu;
1960 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2010 * @param pVCpu Pointer to the VMCPU.
2017 VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2022 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2027 State.pVCpu = pVCpu;
2038 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2041 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2043 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2081 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2128 * @param pVCpu Pointer to the VMCPU.
2131 VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2133 Assert(!pVCpu->cpum.s.fRawEntered);
2134 Assert(!pVCpu->cpum.s.fRemEntered);
2139 *puCpl = CPUMGetGuestCPL(pVCpu);
2144 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2145 pVCpu->cpum.s.fChanged = 0;
2148 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2151 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2154 pVCpu->cpum.s.fRemEntered = true;
2162 * @param pVCpu Pointer to the VMCPU.
2166 VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2168 Assert(!pVCpu->cpum.s.fRawEntered);
2169 Assert(pVCpu->cpum.s.fRemEntered);
2171 pVCpu->cpum.s.fRemEntered = false;
2190 PVMCPU pVCpu = &pVM->aCpus[i];
2193 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
2194 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2198 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;