7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * SELM - Internal header file.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Copyright (C) 2006-2012 Oracle Corporation
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * available from http://www.virtualbox.org. This file is free software;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * you can redistribute it and/or modify it under the terms of the GNU
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * General Public License (GPL) as published by the Free Software
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Checks if a shadow descriptor table entry is good for the given segment
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * register.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @returns @c true if good, @c false if not.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pSReg The segment register.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pShwDesc The shadow descriptor table entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param iSReg The segment register index (X86_SREG_XXX).
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param uCpl The CPL.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: System descriptor\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: Stack must be writable\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if (uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: CS needs code segment\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync else if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: iSReg=%u execute only\n", iSReg));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ( (pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync && ( ( (pSReg->Sel & X86_SEL_RPL) > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync && (pSReg->Sel & X86_SEL_RPL) != pShwDesc->Gen.u1Available )
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync || uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available ) )
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsShwDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u\n", iSReg,
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available, uCpl, pSReg->Sel & X86_SEL_RPL));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return true;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Checks if a guest descriptor table entry is good for the given segment
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * register.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @returns @c true if good, @c false if not.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pVCpu The current virtual CPU.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pSReg The segment register.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pGstDesc The guest descriptor table entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param iSReg The segment register index (X86_SREG_XXX).
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param uCpl The CPL.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: System descriptor\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: Stack must be writable\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pGstDesc->Gen.u2Dpl));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: CS needs code segment\n"));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync else if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: iSReg=%u execute only\n", iSReg));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ( (pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync && ( ( (pSReg->Sel & X86_SEL_RPL) > pGstDesc->Gen.u2Dpl
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsGstDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u InRawMode=%u\n", iSReg,
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu)));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return true;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Converts a guest GDT or LDT entry to a shadow table entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pVM The VM handle.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pDesc Guest entry on input, shadow entry on return.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECL_FORCE_INLINE(void) selmGuestToShadowDesc(PVM pVM, PX86DESC pDesc)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Code and data selectors are generally 1:1, with the
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * 'little' adjustment we do for DPL 0 selectors.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Hack for A-bit against Trap E on read-only GDT.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync /** @todo Fix this by loading ds and cs before turning off WP. */
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * All DPL 0 code and data segments are squeezed into DPL 1.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * We're skipping conforming segments here because those
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * cannot give us any trouble.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * System type selectors are marked not present.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Recompiler or special handling is required for these.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync /** @todo what about interrupt gates and rawr0? */
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Checks if a segment register is stale given the shadow descriptor table
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @returns @c true if stale, @c false if not.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pSReg The segment register.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pShwDesc The shadow descriptor entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param iSReg The segment register number (X86_SREG_XXX).
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECLINLINE(bool) selmIsSRegStale32(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ( pSReg->Attr.n.u1Present != pShwDesc->Gen.u1Present
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync || pSReg->Attr.n.u1DescType != pShwDesc->Gen.u1DescType
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync || pSReg->Attr.n.u1DefBig != pShwDesc->Gen.u1DefBig
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync || pSReg->Attr.n.u1Granularity != pShwDesc->Gen.u1Granularity
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync || pSReg->Attr.n.u2Dpl != pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc)));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return true;
4816371c73f5c7a1c2f7d301f1861556bff55e81vboxsync Log(("selmIsSRegStale32: base changed (%#llx -> %#x)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc)));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return true;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc)));
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return true;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync return false;
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Loads the hidden bits of a selector register from a shadow descriptor table
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pSReg The segment register in question.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pShwDesc The shadow descriptor table entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECLINLINE(void) selmLoadHiddenSRegFromShadowDesc(PCPUMSELREG pSReg, PCX86DESC pShwDesc)
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync Assert(pSReg->Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
a2c0b38648fa3620ea46f884eb614abbf00c6759vboxsync/** @todo VBOX_WITH_RAW_RING1 */
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * Loads the hidden bits of a selector register from a guest descriptor table
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pVCpu The current virtual CPU.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pSReg The segment register in question.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync * @param pGstDesc The guest descriptor table entry.
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncDECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc)
a2c0b38648fa3620ea46f884eb614abbf00c6759vboxsync/** @todo VBOX_WITH_RAW_RING1 */
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu))
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsync#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */