Lines Matching refs:pVCpu
101 static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu);
323 PVMCPU pVCpu = VMMGetCpu(pVM);
324 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
325 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
737 PVMCPU pVCpu = VMMGetCpu(pVM);
738 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
739 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
751 PVMCPU pVCpu = &pVM->aCpus[i];
752 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
773 * @param pVCpu VMCPU Handle.
775 REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu)
805 TMR3NotifyResume(pVM, pVCpu);
806 TMR3NotifySuspend(pVM, pVCpu);
900 * @param pVCpu VMCPU Handle.
902 REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu)
907 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
922 rc = REMR3State(pVM, pVCpu);
936 TMNotifyStartOfExecution(pVCpu);
939 TMNotifyEndOfExecution(pVCpu);
1037 rc2 = REMR3StateBack(pVM, pVCpu);
1053 * @param pVCpu The Virtual CPU handle.
1055 static int remR3RunLoggingStep(PVM pVM, PVMCPU pVCpu)
1076 remR3StateUpdate(pVM, pVCpu);
1080 pVCpu->idCpu,
1088 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
1093 TMNotifyStartOfExecution(pVCpu);
1104 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
1121 TMNotifyEndOfExecution(pVCpu);
1131 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1134 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1164 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1168 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1256 * @param pVCpu VMCPU Handle.
1258 REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu)
1263 return remR3RunLoggingStep(pVM, pVCpu);
1268 TMNotifyStartOfExecution(pVCpu);
1270 TMNotifyEndOfExecution(pVCpu);
1695 /* Assert(env->pVCpu && PGMPhysIsA20Enabled(env->pVCpu));*/
1756 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1763 Assert(env->pVCpu);
1764 rc = PGMInvalidatePage(env->pVCpu, GCPtr);
1768 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1879 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1886 Assert(env->pVCpu);
1887 PGMFlushTLB(env->pVCpu, env->cr[3], fGlobal);
1918 PGMCr0WpEnabled(env->pVCpu);
1928 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1937 Assert(env->pVCpu);
1938 rc = PGMChangeMode(env->pVCpu, env->cr[0], env->cr[4], efer);
2083 * @param pVCpu VMCPU Handle.
2089 REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu)
2102 pVM->rem.s.Env.pVCpu = pVCpu;
2103 pCtx = pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2190 fFlags = CPUMR3RemEnter(pVCpu, &uCpl);
2233 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2235 RTGCPTR InhibitPC = EMGetInhibitInterruptsPC(pVCpu);
2241 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2247 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2253 bool fA20State = PGMPhysIsA20Enabled(pVCpu);
2354 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
2355 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
2390 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, a_pVBoxSReg)) \
2425 rc = TRPMQueryTrap(pVCpu, &u8TrapNo, &enmType);
2431 remR3DumpLnxSyscall(pVCpu);
2432 remR3DumpOBsdSyscall(pVCpu);
2474 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVCpu);
2477 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVCpu);
2492 rc = TRPMResetTrap(pVCpu);
2504 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2510 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_REM);
2529 * @param pVCpu VMCPU Handle.
2531 REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu)
2628 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2642 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2653 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2674 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2705 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2729 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
2730 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2732 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2734 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#2)\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2735 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2742 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2744 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2747 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2763 rc = TRPMAssertTrap(pVCpu, pVM->rem.s.Env.exception_index, enmType);
2770 TRPMSetFaultAddress(pVCpu, pCtx->cr2);
2774 TRPMSetErrorCode(pVCpu, pVM->rem.s.Env.error_code);
2783 CPUMR3RemLeave(pVCpu,
2792 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_REM);
2795 pVM->rem.s.Env.pVCpu = NULL;
2806 static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu)
2882 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2896 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2907 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2928 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2959 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2990 * @param pVCpu The VMCPU handle.
2992 REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu)
2995 remR3StateUpdate(pVM, pVCpu);
3011 * @param pVCpu VMCPU handle.
3015 REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable)
3021 if (pVM->rem.s.Env.pVCpu == pVCpu)
3160 * @param pVCpu VMCPU handle.
3163 REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage)
3821 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1);
3832 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2);
3843 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4);
3855 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1);
3865 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2);
3875 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4);
4042 remR3StateUpdate(pVM, env->pVCpu);
4055 PVMCPU pVCpu = VMMGetCpu(pVM);
4058 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM,
4059 pVCpu->idCpu,
4068 RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
4070 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
4129 PVMCPU pVCpu = cpu_single_env->pVCpu;
4133 Assert(pVCpu);
4138 remR3StateUpdate(pVM, pVCpu);
4151 pVCpu->idCpu,
4217 * @param pVCpu VMCPU Handle.
4221 REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt)
4232 * @param pVCpu VMCPU Handle.
4235 REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM, PVMCPU pVCpu)
4244 * @param pVCpu VMCPU Handle.
4247 REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu)
4265 * @param pVCpu VMCPU Handle.
4268 REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu)
4294 if (pVM->rem.s.Env.pVCpu == pVCpuDst)
4301 LogIt(LOG_INSTANCE, RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: pVCpu:%p != pVCpuDst:%p\n", pVM->rem.s.Env.pVCpu, pVCpuDst));
4463 return TMCpuTickGet(env->pVCpu);
4496 rc = PDMGetInterrupt(env->pVCpu, &u8Interrupt);
4502 if (VMCPU_FF_IS_PENDING(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
4523 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);
4535 int rc = PDMApicSetTPR(env->pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4542 int rc = PDMApicGetTPR(env->pVCpu, &u8, NULL, NULL);
4563 Assert(env->pVCpu);
4564 return CPUMQueryGuestMsr(env->pVCpu, idMsr, puValue) == VINF_SUCCESS ? 0 : -1;
4578 Assert(env->pVCpu);
4579 return CPUMSetGuestMsr(env->pVCpu, idMsr, uValue) == VINF_SUCCESS ? 0 : -1;
4594 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 1);
4609 int rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 2);
4625 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 4);
4640 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1);
4660 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2);
4679 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4);
4716 CPUMGetGuestCpuId(env->pVCpu, idx, idxSub, pEAX, pEBX, pECX, pEDX);
4758 PVMCPU pVCpu;
4802 pVCpu = cpu_single_env->pVCpu;
4803 Assert(pVCpu);
4806 REMR3StateBack(pVM, pVCpu);
4807 EMR3FatalError(pVCpu, VERR_REM_VIRTUAL_CPU_ERROR);
4821 PVMCPU pVCpu;
4833 pVCpu = cpu_single_env->pVCpu;
4834 Assert(pVCpu);
4837 REMR3StateBack(pVM, pVCpu);
4839 EMR3FatalError(pVCpu, rc);
4846 * @param pVCpu VMCPU handle.
4848 void remR3DumpLnxSyscall(PVMCPU pVCpu)
5128 uint32_t uEAX = CPUMGetGuestEAX(pVCpu);
5134 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), CPUMGetGuestEBX(pVCpu), CPUMGetGuestECX(pVCpu),
5135 CPUMGetGuestEDX(pVCpu), CPUMGetGuestESI(pVCpu), CPUMGetGuestEDI(pVCpu), CPUMGetGuestEBP(pVCpu)));
5137 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX));
5146 * @param pVCpu VMCPU handle.
5148 void remR3DumpOBsdSyscall(PVMCPU pVCpu)
5457 uEAX = CPUMGetGuestEAX(pVCpu);
5464 PGMPhysSimpleReadGCPtr(pVCpu, au32Args, CPUMGetGuestESP(pVCpu), sizeof(au32Args));
5466 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
5470 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX);