Searched refs:pVCpu (Results 51 - 75 of 149) sorted by relevance

123456

/vbox/src/VBox/VMM/VMMR0/
H A DPGMR0.cpp63 * @param pVCpu Pointer to the VMCPU.
68 VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu) argument
70 PGM_LOCK_ASSERT_OWNER_EX(pVM, pVCpu);
86 int rc = GMMR0AllocateHandyPages(pVM, pVCpu->idCpu, cPages, cPages, &pVM->pgm.s.aHandyPages[iFirst]);
128 rc = GMMR0AllocateHandyPages(pVM, pVCpu->idCpu, 0, cPages, &pVM->pgm.s.aHandyPages[iFirst]);
179 * @param pVCpu Pointer to the VMCPU.
183 VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PVM pVM, PVMCPU pVCpu) argument
185 PGM_LOCK_ASSERT_OWNER_EX(pVM, pVCpu);
195 int rc = GMMR0AllocateHandyPages(pVM, pVCpu->idCpu, cPages, 0, &pVM->pgm.s.aHandyPages[iFirst]);
210 * @param pVCpu Pointe
215 PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu) argument
420 PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault) argument
548 PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr) argument
[all...]
H A DHMR0.cpp88 DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89 DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90 DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91 DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
227 static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
229 NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
233 static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit) argument
235 NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
269 static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
271 NOREF(pVM); NOREF(pVCpu); NORE
275 hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu) argument
1228 PVMCPU pVCpu = &pVM->aCpus[i]; local
1327 HMR0EnterCpu(PVMCPU pVCpu) argument
1358 HMR0Enter(PVM pVM, PVMCPU pVCpu) argument
1407 HMR0LeaveCpu(PVMCPU pVCpu) argument
1442 PVMCPU pVCpu = (PVMCPU)pvUser; local
1460 HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu) argument
1497 HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
1514 HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
1531 PVMCPU pVCpu = &pVM->aCpus[0]; local
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H A DTRPMR0.cpp44 PVMCPU pVCpu = VMMGetCpu0(pVM); local
45 RTUINT uActiveVector = pVCpu->trpm.s.uActiveVector;
46 pVCpu->trpm.s.uActiveVector = UINT32_MAX;
/vbox/src/VBox/VMM/VMMR3/
H A DVMMGuruMeditation.cpp229 * @param pVCpu Pointer to the VMCPU.
232 VMMR3DECL(void) VMMR3FatalDump(PVM pVM, PVMCPU pVCpu, int rcErr) argument
298 uint32_t uEIP = CPUMGetHyperEIP(pVCpu);
304 int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, &cbInstr);
319 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVCpu), enmType, cbInstr);
327 || pVCpu->vmm.s.CallRing3JmpBufR0.fInRing3Call)
336 pVCpu->vmm.s.CallRing3JmpBufR0.SavedEsp,
337 pVCpu->vmm.s.CallRing3JmpBufR0.SavedEbp,
338 pVCpu->vmm.s.CallRing3JmpBufR0.SpResume,
339 pVCpu
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H A DPGM.cpp665 static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
1254 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
1255 PPGMCPU pPGM = &pVCpu->pgm.s;
1257 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1259 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1276 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1446 PVMCPU pVCpu = &pVM->aCpus[i]; local
1447 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1518 PVMCPU pVCpu = &pVM->aCpus[i]; local
1520 pVCpu
2181 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local
2299 PVMCPU pVCpu = &pVM->aCpus[i]; local
2477 PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu) argument
2532 PVMCPU pVCpu = &pVM->aCpus[i]; local
2547 PVMCPU pVCpu = &pVM->aCpus[i]; local
2566 PVMCPU pVCpu = &pVM->aCpus[i]; local
2750 PVMCPU pVCpu = &pVM->aCpus[0]; local
3094 pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst) argument
3369 PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode) argument
3662 pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu) argument
3683 pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu) argument
3704 pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu) argument
3763 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp)); local
3792 PVMCPU pVCpu = VMMGetCpu(pVM); local
3836 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp)); local
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H A DDBGFCpu.cpp45 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local
46 *penmMode = CPUMGetGuestMode(pVCpu);
83 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local
84 *pfIn64BitCode = CPUMIsGuestIn64BitCode(pVCpu);
H A DVMEmt.cpp231 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
233 && VMCPUSTATE_IS_STARTED(VMCPU_GET_STATE(pVCpu)))
235 rc = EMR3ExecuteVM(pVM, pVCpu);
237 if (EMGetState(pVCpu) == EMSTATE_GURU_MEDITATION)
324 PVMCPU pVCpu = pUVCpu->pVCpu; local
341 || VMCPU_FF_IS_PENDING(pVCpu, fMask))
344 TMTimerPollGIP(pVM, pVCpu, &u64NanoTS);
346 || VMCPU_FF_IS_PENDING(pVCpu, fMask))
480 PVMCPU pVCpu local
666 PVMCPU pVCpu = pUVCpu->pVCpu; local
767 PVMCPU pVCpu = VMMGetCpu(pVM); local
915 PVMCPU pVCpu = pUVCpu->pVCpu; local
1051 VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, bool fIgnoreInterrupts) argument
1139 PVMCPU pVCpu = pUVCpu->pVCpu; local
1200 vmR3SetHaltMethodCallback(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
[all...]
/vbox/src/VBox/VMM/VMMAll/
H A DPDMAll.cpp42 * @param pVCpu Pointer to the VMCPU.
45 VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt) argument
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
54 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
60 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, &uTagSrc);
66 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
74 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
76 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
86 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWOR
232 PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base) argument
263 PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base) argument
286 PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending) argument
309 PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR) argument
336 PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIrq) argument
[all...]
H A DPDMAllCritSect.cpp75 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu);
76 RTNATIVETHREAD hNativeSelf = pVCpu->hNativeThread; Assert(hNativeSelf != NIL_RTNATIVETHREAD);
193 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu); local
194 rc = VMMRZCallRing3(pVM, pVCpu, VMMCALLRING3_VM_R0_PREEMPT, NULL);
299 PVMCPU pVCpu = VMMGetCpu(pVM);
300 HMR0Leave(pVM, pVCpu);
306 HMR0Enter(pVM, pVCpu);
328 PVMCPU pVCpu
659 PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu); local
705 PDMCritSectIsOwnerEx(PCPDMCRITSECT pCritSect, PVMCPU pVCpu) argument
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H A DIOMAllMMIO.cpp276 static int iomMMIODoWrite(PVM pVM, PVMCPU pVCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cb) argument
282 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhysFault, pRange);
492 DECLINLINE(int) iomMMIODoRead(PVM pVM, PVMCPU pVCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhys, void *pvValue, unsigned cbValue) argument
498 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhys, pRange);
577 * @param pVCpu Pointer to the virtual CPU structure of the caller.
583 static int iomInterpretMOVxXRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, argument
596 int rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &u64Data, cb);
638 * @param pVCpu Pointer to the virtual CPU structure of the caller.
644 static int iomInterpretMOVxXWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, argument
658 int rc = iomMMIODoWrite(pVM, pVCpu, pRang
666 iomRamRead(PVMCPU pVCpu, void *pDest, RTGCPTR GCSrc, uint32_t cb) argument
684 iomRamWrite(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void *pvSrc, uint32_t cb) argument
980 iomInterpretSTOS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1114 iomInterpretLODS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1167 iomInterpretCMP(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1228 iomInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PFNEMULATEPARAM3 pfnEmulate) argument
1328 iomInterpretTEST(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1388 iomInterpretBT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1433 iomInterpretXCHG(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1507 iomMMIOHandler(PVM pVM, PVMCPU pVCpu, uint32_t uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault, void *pvUser) argument
1759 IOMMMIOPhysHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault) argument
1802 PVMCPU pVCpu = VMMGetCpu(pVM); local
1857 IOMMMIORead(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue) argument
1989 IOMMMIOWrite(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue) argument
2110 IOMInterpretINSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer) argument
2225 IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
2274 IOMInterpretOUTSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer) argument
2394 IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
2442 PVMCPU pVCpu = VMMGetCpu(pVM); local
2511 IOMMMIOMapMMIOHCPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint64_t fPageFlags) argument
2565 PVMCPU pVCpu = VMMGetCpu(pVM); local
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H A DPGMAllMap.cpp280 PVMCPU pVCpu = VMMGetCpu0(pVM);
281 if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
284 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
302 PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(pVCpu);
310 pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
324 PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
333 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
337 if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
341 PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
347 int rc = pgmShwSyncPaePDPtr(pVCpu, iPdP
440 PVMCPU pVCpu = VMMGetCpu0(pVM); local
557 pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE) argument
642 PVMCPU pVCpu = VMMGetCpu0(pVM); local
682 PVMCPU pVCpu = VMMGetCpu0(pVM); local
747 PVMCPU pVCpu = &pVM->aCpus[0]; local
840 PVMCPU pVCpu = &pVM->aCpus[0]; local
[all...]
H A DPGMAllShw.h174 PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
175 PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
184 * @param pVCpu Pointer to the VMCPU.
191 PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
194 NOREF(pVCpu); NOREF(GCPtr); NOREF(pfFlags); NOREF(pHCPhys);
198 PVM pVM = pVCpu->CTX_SUFF(pVM);
209 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
215 int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
225 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
238 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPt
[all...]
/vbox/include/VBox/vmm/
H A Dtm.h83 VMMDECL(void) TMNotifyStartOfExecution(PVMCPU pVCpu); variable
84 VMMDECL(void) TMNotifyEndOfExecution(PVMCPU pVCpu); variable
85 VMM_INT_DECL(void) TMNotifyStartOfHalt(PVMCPU pVCpu); variable
86 VMM_INT_DECL(void) TMNotifyEndOfHalt(PVMCPU pVCpu); variable
88 VMMR3DECL(int) TMR3NotifySuspend(PVM pVM, PVMCPU pVCpu);
89 VMMR3DECL(int) TMR3NotifyResume(PVM pVM, PVMCPU pVCpu);
93 VMM_INT_DECL(uint32_t) TMCalcHostTimerFrequency(PVM pVM, PVMCPU pVCpu);
134 VMMDECL(uint64_t) TMCpuTickGet(PVMCPU pVCpu); variable
135 VMM_INT_DECL(uint64_t) TMCpuTickGetNoCheck(PVMCPU pVCpu); variable
136 VMM_INT_DECL(bool) TMCpuTickCanUseRealTSC(PVM pVM, PVMCPU pVCpu, uint64_
140 VMM_INT_DECL(uint64_t) TMCpuTickGetLastSeen(PVMCPU pVCpu); variable
142 VMM_INT_DECL(bool) TMCpuTickIsTicking(PVMCPU pVCpu); variable
[all...]
H A Dselm.h50 VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap);
53 VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu);
75 VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags,
77 VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, uint32_t fFlags,
79 VMMDECL(int) SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS,
82 VMM_INT_DECL(void) SELMLoadHiddenSelectorReg(PVMCPU pVCpu, PCCPUMCTX pCtx, PCPUMSELREG pSReg);
96 VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu);
97 VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu);
99 VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo);
H A Dpgm.h151 * @todo Add pVCpu, possibly replacing pVM.
187 * @todo Add pVCpu, possibly replacing pVM.
208 * @todo Add pVCpu, possibly replacing pVM.
296 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu); variable
297 VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
299 VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
303 VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
304 VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
305 VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
306 VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPT
343 VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu); variable
344 VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu); variable
345 VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu); variable
366 VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu); variable
393 VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu); variable
394 VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu); variable
395 VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu); variable
396 VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu); variable
437 VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu); variable
438 VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu); variable
[all...]
H A Diom.h271 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue);
272 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue);
273 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
274 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
275 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb);
276 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb);
277 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
278 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer);
279 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
280 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCOR
[all...]
/vbox/src/VBox/VMM/VMMRC/
H A DSELMRC.cpp60 * @param pVCpu The current virtual CPU.
66 static VBOXSTRICTRC selmRCSyncGDTEntry(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry) argument
68 Log2(("GDT %04X LDTR=%04X\n", iGDTEntry, CPUMGetGuestLDTR(pVCpu)));
74 CPUMGetGuestGDTR(pVCpu, &GdtrGuest);
87 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, (uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC));
90 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
91 VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3); /* paranoia */
114 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
115 VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
138 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu); Asser
185 selmRCSyncGDTSegRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry) argument
240 PVMCPU pVCpu = VMMGetCpu0(pVM); local
355 PVMCPU pVCpu = VMMGetCpu0(pVM); local
386 PVMCPU pVCpu = VMMGetCpu0(pVM); local
[all...]
H A DMMRamRC.cpp86 PVMCPU pVCpu = VMMGetCpu0(pVM); local
91 TRPMSaveTrap(pVCpu);
125 TRPMRestoreTrap(pVCpu);
144 PVMCPU pVCpu = VMMGetCpu0(pVM); local
145 TRPMSaveTrap(pVCpu); /* save the current trap info, because it will get trashed if our access failed. */
151 TRPMRestoreTrap(pVCpu);
H A DTRPMRC.cpp83 PVMCPU pVCpu = VMMGetCpu0(pVM); local
86 TRPMResetTrap(pVCpu);
106 PVMCPU pVCpu = VMMGetCpu0(pVM); local
108 RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
126 int rc = EMInterpretInstructionEx(pVM, pVCpu, pRegFrame, pvFault, &cb);
148 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
169 PVMCPU pVCpu = VMMGetCpu0(pVM); local
185 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL);
H A DCPUMRC.cpp92 PVMCPU pVCpu = VMMGetCpu0(pVM); local
93 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
94 uint8_t const uRawCpl = CPUMGetGuestCPL(pVCpu);
95 uint32_t const u32EFlags = CPUMRawGetEFlags(pVCpu);
106 AssertMsg(CPUMIsGuestInRawMode(pVCpu), ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
115 * @param pVCpu The current virtual CPU.
121 VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) argument
145 if (pVCpu->cpum.s.fRawEntered)
148 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) )
175 * @param pVCpu Pointe
181 CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore) argument
[all...]
/vbox/src/VBox/VMM/include/
H A DHMInternal.h63 * @param pVCpu Pointer to the VMCPU.
66 #define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71 * @param pVCpu Pointer to the VMCPU.
74 #define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79 * @param pVCpu Pointer to the VMCPU.
82 #define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
88 * @param pVCpu Pointe
[all...]
H A DGIMKvmInternal.h254 VMMR3_INT_DECL(int) gimR3KvmEnableSystemTime(PVM pVM, PVMCPU pVCpu, PGIMKVMCPU pKvmCpu, uint8_t fFlags);
259 VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu); variable
260 VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
261 VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
262 VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
263 VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu); variable
264 VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
H A DEMInternal.h461 int emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
462 int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
463 int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
464 int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
465 EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
466 int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
467 int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
468 int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
469 int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
470 int emR3RawStep(PVM pVM, PVMCPU pVCpu);
[all...]
/vbox/src/VBox/VMM/VMMRZ/
H A DDBGFRZ.cpp41 * @param pVCpu Pointer to the VMCPU.
46 VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping) argument
66 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
67 pVCpu->dbgf.s.fSingleSteppingRaw = false;
81 && (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
83 pVCpu->dbgf.s.fSingleSteppingRaw = false;
111 * @param pVCpu Pointer to the VMCPU.
114 VMMRZ_INT_DECL(int) DBGFRZTrap03Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) argument
129 int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
144 pVCpu
[all...]
/vbox/src/VBox/VMM/include/internal/
H A Dpgm.h67 VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
70 VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
71 VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);

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