Searched refs:PVMCPU (Results 1 - 25 of 150) sorted by relevance

123456

/vbox/include/VBox/vmm/
H A Dtrpm.h71 VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, PTRPMEVENT penmType);
72 VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu);
73 VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu);
74 VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu);
75 VMMDECL(uint8_t) TRPMGetInstrLength(PVMCPU pVCpu);
76 VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu);
77 VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType);
78 VMMDECL(int) TRPMAssertXcptPF(PVMCPU pVCpu, RTGCUINTPTR uCR2, RTGCUINT uErrorCode);
79 VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode);
80 VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCp
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H A Dcpum.h1015 VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1016 VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1017 VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1018 VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1019 VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1020 VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1021 VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1022 VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1023 VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1024 VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCp
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H A Dvmm.h132 typedef DECLCALLBACK(int) FNVMMR0CALLRING3NOTIFICATION(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser);
147 typedef DECLCALLBACK(VBOXSTRICTRC) FNVMMEMTRENDEZVOUS(PVM pVM, PVMCPU pVCpu, void *pvUser);
260 VMM_INT_DECL(RTRCPTR) VMMGetStackRC(PVMCPU pVCpu);
262 VMMDECL(PVMCPU) VMMGetCpu(PVM pVM);
263 VMMDECL(PVMCPU) VMMGetCpu0(PVM pVM);
264 VMMDECL(PVMCPU) VMMGetCpuById(PVM pVM, VMCPUID idCpu);
265 VMMR3DECL(PVMCPU) VMMR3GetCpuByIdU(PUVM pVM, VMCPUID idCpu);
268 VMM_INT_DECL(bool) VMMIsInRing3Call(PVMCPU pVCpu);
271 VMM_INT_DECL(void) VMMHypercallsEnable(PVMCPU pVCpu);
272 VMM_INT_DECL(void) VMMHypercallsDisable(PVMCPU pVCp
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H A Diem.h63 VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu);
64 VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
65 VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
67 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
68 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
70 VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu);
71 VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu);
72 VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
80 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
82 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCp
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H A Dhm.h141 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
143 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
145 VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable);
146 VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu);
147 VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu);
150 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
180 VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
182 VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
198 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
199 VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCp
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H A Dem.h102 VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu);
103 VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
172 VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
173 VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
174 VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
175 VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
177 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
178 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
179 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
183 VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCp
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H A Drem.h51 VMMDECL(void) REMNotifyHandlerPhysicalFlushIfAlmostFull(PVM pVM, PVMCPU pVCpu);
64 REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu);
65 REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu);
66 REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu);
69 REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu);
70 REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu);
71 REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu);
72 REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable);
75 REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage);
87 REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCp
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H A Dgim.h107 typedef DECLCALLBACK(int) FNGIMHYPERCALL(PVMCPU pVCpu, PCPUMCTX pCtx);
120 typedef DECLCALLBACK(int) FNGIMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
134 typedef DECLCALLBACK(int) FNGIMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
174 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu);
175 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
176 VMM_INT_DECL(int) GIMXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
177 VMM_INT_DECL(bool) GIMShouldTrapXcptUD(PVMCPU pVCpu);
178 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
179 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
H A Dcpumdis.h40 VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
H A Dtm.h83 VMMDECL(void) TMNotifyStartOfExecution(PVMCPU pVCpu);
84 VMMDECL(void) TMNotifyEndOfExecution(PVMCPU pVCpu);
85 VMM_INT_DECL(void) TMNotifyStartOfHalt(PVMCPU pVCpu);
86 VMM_INT_DECL(void) TMNotifyEndOfHalt(PVMCPU pVCpu);
88 VMMR3DECL(int) TMR3NotifySuspend(PVM pVM, PVMCPU pVCpu);
89 VMMR3DECL(int) TMR3NotifyResume(PVM pVM, PVMCPU pVCpu);
93 VMM_INT_DECL(uint32_t) TMCalcHostTimerFrequency(PVM pVM, PVMCPU pVCpu);
134 VMMDECL(uint64_t) TMCpuTickGet(PVMCPU pVCpu);
135 VMM_INT_DECL(uint64_t) TMCpuTickGetNoCheck(PVMCPU pVCpu);
136 VMM_INT_DECL(bool) TMCpuTickCanUseRealTSC(PVM pVM, PVMCPU pVCp
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H A Dselm.h50 VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap);
53 VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu);
75 VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags,
77 VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, uint32_t fFlags,
79 VMMDECL(int) SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS,
82 VMM_INT_DECL(void) SELMLoadHiddenSelectorReg(PVMCPU pVCpu, PCCPUMCTX pCtx, PCPUMSELREG pSReg);
96 VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu);
97 VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu);
99 VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo);
H A Dpgm.h296 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
297 VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
299 VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
303 VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
304 VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
305 VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
306 VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
307 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
318 VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
319 VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCp
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H A Diom.h271 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue);
272 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue);
273 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
274 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
275 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb);
276 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb);
277 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
278 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer);
279 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
280 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, PVMCPU pVCp
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/vbox/src/VBox/VMM/VMMR0/
H A DPGMR0Bth.h23 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
H A DHMSVMR0.h42 VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
43 VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
50 VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
51 VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu);
54 DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
55 VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
69 DECLASM(int) SVMR0VMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
82 DECLASM(int) SVMR0VMRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
H A DHMVMXR0.h31 VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
32 VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
41 VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu);
42 VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
43 DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
44 DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
48 DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
49 VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
55 VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
57 DECLINLINE(int) VMXReadCachedVmcsEx(PVMCPU pVCp
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/vbox/src/VBox/VMM/VMMAll/
H A DCPUMAllMsrs.cpp69 typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
88 typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
102 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
110 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
118 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
125 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
141 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
149 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
157 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
165 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCp
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H A DCPUMAllRegs.cpp92 static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
145 VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
157 VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
173 VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
184 VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
190 VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
197 VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
204 VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
214 VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
220 VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCp
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H A DCPUMStack.cpp33 VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32)
H A DHMAll.cpp63 static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
88 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
112 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu)
136 static void hmR0PokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu)
187 static void hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat)
222 PVMCPU pVCpu = &pVM->aCpus[idCpu];
259 PVMCPU pVCpu = &pVM->aCpus[idCpu];
381 PVMCPU pVCpu = &pVM->aCpus[idCpu];
417 PVMCPU pVCpu = VMMGetCpu(pVM);
428 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCp
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H A DVMMAll.cpp179 VMM_INT_DECL(RTRCPTR) VMMGetStackRC(PVMCPU pVCpu)
215 PVMCPU pVCpu = &pVM->aCpus[idCpu];
228 PVMCPU pVCpu = &pVM->aCpus[idCpu];
250 VMMDECL(PVMCPU) VMMGetCpu(PVM pVM)
277 PVMCPU pVCpu = &pVM->aCpus[idCpu];
291 PVMCPU pVCpu = &pVM->aCpus[idCpu];
311 VMMDECL(PVMCPU) VMMGetCpu0(PVM pVM)
327 VMMDECL(PVMCPU) VMMGetCpuById(PVM pVM, RTCPUID idCpu)
367 VMM_INT_DECL(bool) VMMIsInRing3Call(PVMCPU pVCpu)
443 VMM_INT_DECL(void) VMMHypercallsEnable(PVMCPU pVCp
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/vbox/src/VBox/VMM/VMMR3/
H A DPGMGst.h25 PGM_GST_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
26 PGM_GST_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
27 PGM_GST_DECL(int, Exit)(PVMCPU pVCpu);
30 PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
31 PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
32 PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
93 PGM_GST_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
110 PGM_GST_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
130 PGM_GST_DECL(int, Exit)(PVMCPU pVCpu)
/vbox/src/VBox/VMM/include/internal/
H A Dpgm.h67 VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
70 VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
71 VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
/vbox/src/VBox/VMM/VMMRZ/
H A DVMMRZ.cpp46 VMMRZDECL(int) VMMRZCallRing3(PVM pVM, PVMCPU pVCpu, VMMCALLRING3 enmOperation, uint64_t uArg)
128 VMMRZDECL(void) VMMRZCallRing3Disable(PVMCPU pVCpu)
162 VMMRZDECL(void) VMMRZCallRing3Enable(PVMCPU pVCpu)
194 VMMRZDECL(bool) VMMRZCallRing3IsEnabled(PVMCPU pVCpu)
211 VMMRZDECL(int) VMMRZCallRing3SetNotification(PVMCPU pVCpu, R0PTRTYPE(PFNVMMR0CALLRING3NOTIFICATION) pfnCallback, RTR0PTR pvUser)
230 VMMRZDECL(void) VMMRZCallRing3RemoveNotification(PVMCPU pVCpu)
242 VMMRZDECL(bool) VMMRZCallRing3IsNotificationSet(PVMCPU pVCpu)
/vbox/src/VBox/VMM/include/
H A DGIMKvmInternal.h254 VMMR3_INT_DECL(int) gimR3KvmEnableSystemTime(PVM pVM, PVMCPU pVCpu, PGIMKVMCPU pKvmCpu, uint8_t fFlags);
259 VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu);
260 VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
261 VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
262 VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
263 VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu);
264 VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);

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