Lines Matching refs:PVMCPU
141 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
143 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
145 VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable);
146 VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu);
147 VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu);
150 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
180 VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
182 VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
198 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
199 VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
200 VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
201 VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
206 VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
207 VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
211 VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx);
228 VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
234 VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
237 VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu);
238 VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu);
239 VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
240 VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
242 VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
245 VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);