Searched refs:VLV_DISPLAY_BASE (Results 1 - 4 of 4) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Di915_reg.h431 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
441 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
442 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
477 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
811 #define VLV_DISPLAY_BASE 0x180000 macro
818 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
820 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
821 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
822 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
823 #define VLV_IMR (VLV_DISPLAY_BASE
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H A Dintel_i2c.c541 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
H A Di915_drv.c265 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .display_mmio_offset = VLV_DISPLAY_BASE,
H A Dintel_display.c9099 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9100 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9102 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9103 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9105 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9106 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);

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