Lines Matching refs:VLV_DISPLAY_BASE
431 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
441 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
442 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
477 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
811 #define VLV_DISPLAY_BASE 0x180000
818 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
820 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
821 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
822 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
823 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
824 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
825 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1455 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1458 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1870 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
3057 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3071 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3125 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
3131 #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3582 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3601 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3602 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3603 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3604 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3605 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3606 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3607 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3608 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3609 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3610 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3611 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3613 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3614 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3615 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3616 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3617 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3618 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3619 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3620 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3621 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3622 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3623 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3624 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
3645 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4123 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4124 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4125 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
4127 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4128 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4129 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
4392 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4393 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4394 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4395 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4396 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4398 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4399 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4400 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4401 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4402 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)