Searched refs:x7 (Results 1 - 25 of 503) sorted by relevance

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/illumos-gate/usr/src/cmd/dtrace/demo/dtrace/
H A Dbegin.d41 printf("mmap with prot = %s", prot[arg2 & 0x7]);
/illumos-gate/usr/src/uts/common/sys/contract/
H A Ddevice.h46 #define CT_DEV_ALLEVENT 0x7
54 #define CTDP_ALLPARAMS 0x7
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dmem_cache_ioctl.h34 #define PN_ECSTATE_MASK 0x7 /* three bit field */
42 #define PN_ECSTATE_RES 0x7 /* reserved */
H A Dcpu_impl.h100 #define OLYMPUS_REV_MASK(x) (((x) >> 28) & 0x7)
106 #define JUPITER_IMPL 0x7
/illumos-gate/usr/src/boot/sys/sys/
H A Dbitstring.h47 (1 << ((bit)&0x7))
81 _name[_startbyte] &= ((0xff >> (8 - (_start&0x7))) | \
82 (0xff << ((_stop&0x7) + 1))); \
84 _name[_startbyte] &= 0xff >> (8 - (_start&0x7)); \
87 _name[_stopbyte] &= 0xff << ((_stop&0x7) + 1); \
98 _name[_startbyte] |= ((0xff << (_start&0x7)) & \
99 (0xff >> (7 - (_stop&0x7)))); \
101 _name[_startbyte] |= 0xff << ((_start)&0x7); \
104 _name[_stopbyte] |= 0xff >> (7 - (_stop&0x7)); \
/illumos-gate/usr/src/uts/common/sys/sata/
H A Dsata_blacklist.h55 {0x47261095, 0x0, 0x7, 0x5}, /* Silicon Image 4726, 5 ports. */
H A Dsata_satl.h50 #define SATL_APT_P_DMA_QUEUED 0x7 /* DMA Queued */
/illumos-gate/usr/src/uts/sun4u/sys/i2c/clients/
H A Dpic16f819_reg.h41 #define PIC16F819_FAN_STATUS_MASK 0x7
/illumos-gate/usr/src/uts/common/sys/
H A Dagpgart.h116 #define AGPSTAT_RATE_MASK 0x7
122 #define AGPSTAT_ARQSZ_MASK (0x7 << 13) /* target only */
123 #define AGPSTAT_CAL_MASK (0x7 << 10)
136 #define AGPCMD_RATE_MASK 0x7
138 #define AGP3_CMD_ARQSZ_MASK (0x7 << 13) /* master only */
139 #define AGP3_CMD_CAL_MASK (0x7 << 10) /* target only */
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dvsc7326_reg.h39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
45 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
46 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
47 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
48 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
49 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
50 #define REG_SI_TRANSFER_SEL CRA(0x7,
[all...]
H A Dvsc7321_reg.h39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
45 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
46 #define REG_CRC_CNT CRA(0x7,0xf,0x0a) /* CRC error count */
47 #define REG_CRC_CFG CRA(0x7,0xf,0x0b) /* CRC config */
48 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
49 #define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
50 #define REG_SYS_CLK_SELECT CRA(0x7,
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/illumos-gate/usr/src/uts/common/io/hme/
H A Dhme_phy.h132 #define PHY_ANAR_RES1 (0x7 << 10) /* 10-12 reserved */
163 #define PHY_ANLPAR_RES1 (0x7 << 10) /* 10-12 reserved */
245 #define PHY_CSCR_RES2 (0x7 << 8) /* 8-10 reserved */
270 #define PHY_LBREMR_RES1 (0x7 << 5) /* Reserved */
/illumos-gate/usr/src/uts/sun/io/eri/
H A Deri_phy.h132 #define PHY_ANAR_RES1 (0x7 << 10) /* 10-12 reserved */
163 #define PHY_ANLPAR_RES1 (0x7 << 10) /* 10-12 reserved */
246 #define PHY_CSCR_RES2 (0x7 << 8) /* 8-10 reserved */
271 #define PHY_LBREMR_RES1 (0x7 << 5) /* Reserved */
/illumos-gate/usr/src/uts/sun4u/serengeti/sys/
H A Dsgevents.h73 #define SC_EVENT_ENV 0x7
/illumos-gate/usr/src/uts/sun4u/starcat/sys/
H A Dsckm_msg.h94 #define SCKM_ERR_SADB_TIMEOUT 0x7 /* no response from key engine */
H A Dstarcat.h112 #define STARCAT_CPUID_TO_AGENT(p) ((p) & 0x7)
116 ((((e) & 0x1f) << 5) | (((s) & 0x1) << 3) | ((a) & 0x7))
/illumos-gate/usr/src/uts/sun4u/opl/sys/
H A Doplkm_msg.h84 #define OKM_ERR_SADB_TIMEOUT 0x7 /* no response from key engine */
/illumos-gate/usr/src/boot/lib/libc/string/
H A Dswab.c55 for (; n & 0x7; --n)
/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Dsil3xxx.c122 fifo_cnt_ctl = (fifo_cnt_ctl & ~0x7) | (frrc & 0x7);
/illumos-gate/usr/src/uts/common/sys/dcam/
H A Ddcam1394_io.h57 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_5 0x7
100 #define DCAM1394_SUBPARAM_FRAME_RATE_1 0x7
101 #define DCAM1394_SUBPARAM_FRAME_RATE_7_5_FPS 0x7
154 #define DCAM1394_FRAME_RATE_1 0x7
155 #define DCAM1394_7_5_FPS 0x7
/illumos-gate/usr/src/common/crypto/chacha/
H A Dchacha.c90 u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15; local
129 x7 = j7;
142 QUARTERROUND( x3, x7,x11,x15)
145 QUARTERROUND( x2, x7, x8,x13)
155 x7 = PLUS(x7,j7);
173 x7 = XOR(x7,U8TO32_LITTLE(m + 28));
197 U32TO8_LITTLE(c + 28,x7);
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_regs.h188 #define JBUS_CHANGE_INITIATION_CONTROL_CDELAY_MASK 0x7
322 #define JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_S_INT_EN_MASK 0x7
353 #define JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_P_INT_EN_MASK 0x7
388 #define JBC_ERROR_LOG_ENABLE_SPARE_LOG_EN_MASK 0x7
420 #define JBC_INTERRUPT_ENABLE_SPARE_S_INT_EN_MASK 0x7
451 #define JBC_INTERRUPT_ENABLE_SPARE_P_INT_EN_MASK 0x7
483 #define JBC_INTERRUPT_STATUS_SPARE_S_MASK 0x7
514 #define JBC_INTERRUPT_STATUS_SPARE_P_MASK 0x7
546 #define JBC_ERROR_STATUS_CLEAR_SPARE_S_MASK 0x7
577 #define JBC_ERROR_STATUS_CLEAR_SPARE_P_MASK 0x7
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/illumos-gate/usr/src/cmd/picl/plugins/sun4u/snowbird/envmond/
H A Dpicldr.h62 #define SATCPU_STATE_ONLINE 0x7
/illumos-gate/usr/src/cmd/picl/plugins/sun4u/snowbird/lib/libctsmc/
H A Dsmclib.h51 SMC_INVALID_SEQ = 0x7,
/illumos-gate/usr/src/uts/common/sys/usb/hcd/uhci/
H A Duhcipolled.h56 #define MAX_NUM_FOR_KEYBORAD 0x7

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