/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef HME_PHY_H
#define HME_PHY_H
/* DP83840 - 10/100 Mbps Physical layer from National semiconductor */
/*
* MII supports a 16-bit register stack of upto 32, addressable through the
* MDIO and MDC serial port.
*/
/* Registers 7-15 are reserved for future assignments by MII working group */
/* Do not write to these registers */
/* Registers 16-17 are reserved for future assignment by Vendor */
/* Do not write to these registers */
/* Registers 29-31 are reserved for future assignment by Vendor */
/* Do not write to these registers */
/*
* QSI 6612 Physical layer device specific registers.
* Addition Interface Technologies Group (NPG) 8/28/1997.
*/
/* ************************************************************************ */
/* Register 00 Basic Mode Control Register */
/* ************************************************************************ */
/* Register 01 Basic Mode Status Register */
/* ************************************************************************ */
/*
* Registers 2 and 3 provide a 32 bit value which is a unique identifier
* for a particular type of PHY. A 24-bit Organizationally Unique Identifier
* (OUI) is defined with bit 1 as the MSB and bit 24 as the LSB. Bits 3-18 of
* the OUI are found in PHY Identifier Register 1 and bits 19-24 are found in
* PHY Identifier Register 2.
*
* The hexadecimal OUI code for NSC is 0x080017 .
*/
/* Register 02 PHY Identifier Register 1 */
/* Register 03 PHY Identifier Register 2 */
/* ************************************************************************ */
/*
* Register 04 Auto-Negotiation Advertisement Register (nway1Reg)
* This register will hold the different modes of operation to be advertised to
* the far-end PHY.
*/
/* Capability word */
/* <00001> is specified */
/*
* Priority scheme (from highest to lowest) for Auto Link Negotiation:
* 1 - 100Base-TX Full Duplex
* 2 - 100Base-T4
* 3 - 100Base-TX
* 4 - 10Base-T Full Duplex
* 5 - 10Base-T
*/
/* ************************************************************************ */
/*
* Register 05 Auto-Negotiation Link Partner Ability Reg
* This register contains the Link Partners capabilities after NWay
* Auto-Negotiation is complete.
*/
/* capability data word */
/* is specified */
/* ************************************************************************ */
/*
* Register 06 Auto-Negotiation Expansion Register
* This register contains additional status for NWay Auto-Negotiation
*/
/* Next Pages. Should be 0 for DP83840 */
/* ************************************************************************ */
/* Registers 7-15 are reserved for future assignments by MII working group */
/* Do not write to these registers */
/* Registers 16-17 are reserved for future assignment by Vendor */
/* Do not write to these registers */
/* ************************************************************************ */
/*
* Register 18 Disconnect Counter
* This 16-bit counter is incremented for every disconnect event. It rolls over
* when full.
*/
/* ************************************************************************ */
/*
* Register 19 False Carrier Sense Counter
* This 16-bit counter is incremented for each false carrier event (i.e. carrier
* assertion without JK detect). It freezes when full.
*/
/* ************************************************************************ */
/*
* Register 20 NWay Test Register
*/
/* ************************************************************************ */
/*
* Register 21 RX_ER Counter
* This 16-bit counter is incremented once per valid packet (i.e. no collision
* occured during packet reception), if there is one or more receive error
* condition during the packet reception. The counter is incremented at the end
* of the packet reception.
*/
/* ************************************************************************ */
/*
* Register 22 Silicon Revision Register
* Contains information on silicon revision
* This register will be incremented for any change made to the device.
*/
/* ************************************************************************ */
/*
* Register 23 CS Configuration Register
*/
/* in descrambler */
/* ************************************************************************ */
/*
* Register 24 Loopback, Bypass, Receiver Error Mask Reg
* The high byte of this register configures the DP83840 whilst its low byte
* programs the receive error types to be reported in real time as a HEX code
* across the MII RXD<3:0> interface.
*/
/* ************************************************************************ */
/*
* Register 25 PHY Address Register
*/
/*
* The PHYAD<4:0> allow 32 unique PHY addresses. The PHYAD<4:0> share the RX_ER,
* PHYAD3, CRS, ENCSEL ald LBEN pins of the PHY. By patching the PHYAD address
* pins with a light pull-up or pull-down resistor, the PMD address can be
* strobed and stored in these register location during Reset or Power-on reset
* time.
*
* The first PHY address bit transmitted or received is the MSB of the address.
* A PHY connected to a station management entity via an interface connector
* shall always respond to PHY address < 00000 > . A station management entity
* connected to multiple PHY entities must know the appropriate PHY address of
* each PHY entity. PHY address should be set to < 00001 > for a single
* PHY entity. A PHY address of < 00000 > will cause the Isolate bit 0: < 10 >
* to be set to one.
*/
/* ************************************************************************ */
/*
* Register 26 Reserverd for future assignement by vendor
*/
/* ************************************************************************ */
/*
* Register 27 10 Mbps TPI Status Register
*/
/* ************************************************************************ */
/*
* Register 28 10 Mbps Network I/F Configuration Register
*/
/* or xwrap mode */
/* ************************************************************************ */
/* Registers 29-31 are reserved for future assignment by Vendor */
/* Do not write to these registers */
/*
* QSI 6612 Physical layer device specific register bits.
* Addition Interface Technologies Group (NPG) 8/28/1997.
*/
/* ************************************************************************ */
#endif /* HME_PHY_H */