/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_STARCAT_H
#define _SYS_STARCAT_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Manifest constants of Starcat configuration
*/
/* max prealloc spare tsb's */
#define STARCAT_SPARE_TSB_MAX \
/*
* Data bearing mondo vector (DMV) support
*
* For Starcat, we need to add a few extra "hardware" dmv interrupts.
* These actually do not correspond to physical hardware but are used
* by Starcat IDN.
*/
/*
* The CPU ID on starcat looks like this:
*
* 9 5 4 3 2 1 0
* --------------------------------------
* | Expander | | Slot | Core | LPORT |
* --------------------------------------
*
* Expander Starcat has STARCAT_BDSET_MAX (18) expanders.
* Slot Starcat has STARCAT_BDSET_SLOT_MAX (2) slots per expander.
* Slot 0 carries a CPU-MEM board which has 4 processor chips.
* Slot 1 carries an I/O board typically. But it can be
* configured to carry a MAXCAT board which has 2 processor
* chips on board.
* LPORT Port number within the slot for a chip. This is also the
* chip number within the slot. Note that Slot 1 can have only
* 2 chips, but this representation allows for 4. This is just
* the theoretical max.
* Core Core number within the chip.
*
* Currently, the maximum number of cores supported is 2 per chip (on
* Panther and Jaguar).
*
*/
/*
* Macros for manipulating CPU IDs
*/
#define MAKE_CPUID(e, s, a) \
((((e) & 0x1f) << 5) | (((s) & 0x1) << 3) | ((a) & 0x7))
/*
* Definitions for decoding memory controller registers. These values
* are taken from Chapter 9 of the SPARCV9 JSP-1 US-III implementation
* supplement.
*/
/* Starcat has four banks of memory per MC */
/* Use only low bits for local CPU MC ASI */
/* Shifts to access specific fields of the memdecode register */
/* Extract upper mask field from the decode register */
/* Extract upper match field from memdecode register */
/* Size of the range covered by the address mask field */
/* The base PA the memdecode register will respond to */
/*
* Prototypes for functions
*/
extern int set_platform_max_ncpus(void);
extern int plat_max_boards(void);
extern int plat_max_cpu_units_per_board(void);
extern int plat_max_mem_units_per_board(void);
extern int plat_max_io_units_per_board(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYS_STARCAT_H */