/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PX_REGS_H
#define _SYS_PX_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Register tools history */
#pragma ident "@(#)hdgen 1.3 03/11/10"
#pragma ident "@(#)firedefiner.pl 1.7 03/11/19"
/* jcs.csr JCS module defines */
#define JBUS_DEVICE_ID_MR 0
#define FIRE_CONTROL_STATUS_LPDQ 0
#define JBUS_PLL_CONTROL_AND_DTL_CONTROL_CNTLMT 0
#define JBUS_ENERGY_STAR_CONTROL_FULL 0
#define JBUS_CHANGE_INITIATION_CONTROL_CDELAY 0
#define RESET_GENERATION_PO_RST 0
#define RESET_SOURCE_PO_RST 0
#define GPIO_PORT_0_PIN_0_DATA_DATA 0
#define GPIO_PORT_0_PIN_1_DATA_DATA 0
#define GPIO_PORT_0_PIN_2_DATA_DATA 0
#define GPIO_PORT_0_PIN_3_DATA_DATA 0
#define GPIO_PORT_0_DATA_DATA_0 0
#define GPIO_PORT_0_CONTROL_DIR_0 0
#define GPIO_PORT_1_PIN_0_DATA_DATA 0
#define GPIO_PORT_1_PIN_1_DATA_DATA 0
#define GPIO_PORT_1_PIN_2_DATA_DATA 0
#define GPIO_PORT_1_PIN_3_DATA_DATA 0
#define GPIO_PORT_1_DATA_DATA_0 0
#define GPIO_PORT_1_CONTROL_DIR_0 0
#define EBUS_EPROM_TIMING_CONTROL_SETUP_COUNT 0
#define I2C_0_INPUT_MONITOR_SDA 0
#define I2C_0_DATA_DRIVE_SDA 0
#define I2C_0_CLOCK_DRIVE_SCL 0
#define I2C_1_INPUT_MONITOR_SDA 0
#define I2C_1_DATA_DRIVE_SDA 0
#define I2C_1_CLOCK_DRIVE_SCL 0
#define JBUS_PARITY_CONTROL_NEXT_ADDR 0
#define JBUS_SCRATCH_1_DATA 0
#define JBUS_SCRATCH_2_DATA 0
#define JBUS_SCRATCH_PERSISTENT_DATA 0
#define JBC_ERROR_LOG_ENABLE_JTCEER_LOG_EN 0
#define JBC_INTERRUPT_ENABLE_JTCEER_P_INT_EN 0
#define JBC_INTERRUPT_STATUS_JTCEER_P 0
#define JBC_ERROR_STATUS_CLEAR_JTCEER_P 0
#define JBC_ERROR_STATUS_SET_JTCEER_P 0
#define JBC_FATAL_RESET_ENABLE_JTCEER_P_INT_EN 0
#define JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS 0
#define JBCINT_IN_TRANSACTION_ERROR_LOG_2_J_PACK 0
#define JBCINT_OUT_TRANSACTION_ERROR_LOG_ADDRESS 0
#define FATAL_ERROR_LOG_1_DATA 0
#define FATAL_ERROR_LOG_2_J_PACK 0
#define MERGE_TRANSACTION_ERROR_LOG_ADDRESS 0
#define DMCINT_ODCD_ERROR_LOG_ADDRESS 0
#define DMCINT_IDC_ERROR_LOG_TARGID 0
#define CSR_ERROR_LOG_ADDRESS 0
#define JBC_CORE_AND_BLOCK_ERROR_STATUS_DMCINT 0
#define JBC_PERFORMANCE_COUNTER_SELECT_SEL0 0
#define JBC_PERFORMANCE_COUNTER_ZERO_CNT 0
#define JBC_PERFORMANCE_COUNTER_ONE_CNT 0
#define FIRE_AND_JBC_DEBUG_SELECT_A_SIGNAL_SEL 0
#define FIRE_AND_JBC_DEBUG_SELECT_B_SIGNAL_SEL 0
/* iss.csr ISS module defines */
/* Reserved 0x1200 - 0x13f8 */
#define INTERRUPT_CLEAR_ENTRIES_INT_STATE 0
/* Reserved 0x1600 - 0x17f8 */
/* Reserved 0x1808 - 0x19f8 */
#define INTERRUPT_RETRY_TIMER_LIMIT 0
/* Reserved 0x1a08 - 0x1a08 */
#define INTERRUPT_STATE_STATUS_1_STATE 0
#define INTERRUPT_STATE_STATUS_2_STATE 0
/* intx.csr INTX module defines */
#define INTX_STATUS_INT_D 0
#define INT_A_CLEAR_CLR 0
#define INT_B_CLEAR_CLR 0
#define INT_C_CLEAR_CLR 0
#define INT_D_CLEAR_CLR 0
/* eqs.csr EQS module defines */
/* Reserved 0x10008 - 0x10ff8 */
/* Reserved 0x11120 - 0x111f8 */
/* Reserved 0x11320 - 0x113f8 */
#define EVENT_QUEUE_STATE_ENTRIES_STATE 0
/* Reserved 0x11520 - 0x115f8 */
#define EVENT_QUEUE_TAIL_ENTRIES_TAIL 0
/* Reserved 0x11720 - 0x117f8 */
#define EVENT_QUEUE_HEAD_ENTRIES_HEAD 0
/* msi.csr MSI module defines */
#define MSI_MAPPING_ENTRIES_EQNUM 0
/* Reserved 0x20800 - 0x27ff8 */
/* Reserved 0x28800 - 0x2bff8 */
#define INTERRUPT_MONDO_DATA_1_DATA 0
/* mess.csr MESS module defines */
#define ERR_COR_MAPPING_EQNUM 0
#define ERR_NONFATAL_MAPPING_EQNUM 0
#define ERR_FATAL_MAPPING_EQNUM 0
#define PM_PME_MAPPING_EQNUM 0
#define PME_TO_ACK_MAPPING_EQNUM 0
/* ics.csr ICS module defines */
#define IMU_ERROR_LOG_ENABLE_MSI_NOT_EN_LOG_EN 0
#define IMU_INTERRUPT_ENABLE_MSI_NOT_EN_P_INT_EN 0
#define IMU_INTERRUPT_STATUS_MSI_NOT_EN_P 0
#define IMU_ERROR_STATUS_CLEAR_MSI_NOT_EN_P 0
#define IMU_ERROR_STATUS_SET_MSI_NOT_EN_P 0
#define IMU_RDS_ERROR_LOG_MSI_DATA 0
#define IMU_SCS_ERROR_LOG_EQ_NUM 0
#define IMU_EQS_ERROR_LOG_EQ_NUM 0
/* Reserved 0x31040 - 0x317f8 */
#define DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE_IMU 0
#define DMC_CORE_AND_BLOCK_ERROR_STATUS_IMU 0
#define MULTI_CORE_ERROR_STATUS_DMC 0
/* Reserved 0x31818 - 0x31ff8 */
#define IMU_PERFORMANCE_COUNTER_SELECT_SEL0 0
#define IMU_PERFORMANCE_COUNTER_ZERO_CNT 0
#define IMU_PERFORMANCE_COUNTER_ONE_CNT 0
/* Reserved 0x32018 - 0x33ff8 */
/* Reserved 0x34010 - 0x34010 */
#define MEM_64_PCIE_OFFSET_SPARE_STATUS 0
/* csr.csr CSR module defines */
#define MMU_CONTROL_AND_STATUS_TE 0
#define MMU_TSB_CONTROL_TS 0
/* Reserved 0x40010 - 0x400f8 */
#define MMU_TTE_CACHE_INVALIDATE_FLSH_TTE 0
/* Reserved 0x40110 - 0x40ff8 */
#define MMU_ERROR_LOG_ENABLE_EN 0
#define MMU_INTERRUPT_ENABLE_EN_P 0
#define MMU_INTERRUPT_STATUS_ERR_P 0
#define MMU_INTERRUPT_STATUS_BYP_ERR_P 0
#define MMU_ERROR_STATUS_CLEAR_BYP_ERR_P 0
#define MMU_ERROR_STATUS_SET_BYP_ERR_P 0
#define MMU_TRANSLATION_FAULT_STATUS_ID 0
/* Reserved 0x41038 - 0x41ff8 */
#define MMU_PERFORMANCE_COUNTER_SELECT_SEL0 0
#define MMU_PERFORMANCE_COUNTER_ZERO_CNT 0
#define MMU_PERFORMANCE_COUNTER_ONE_CNT 0
/* Reserved 0x42018 - 0x43ff8 */
/* Reserved 0x44008 - 0x45ff8 */
#define MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_VLD 0
/* Reserved 0x46200 - 0x46ff8 */
#define MMU_TTE_CACHE_PHYSICAL_TAG_ENTRIES_VLD 0
/* Reserved 0x47200 - 0x47ff8 */
#define MMU_TTE_CACHE_DATA_ENTRIES_VLD 0
/* cib.csr CIB module defines */
/* Reserved 0x50008 - 0x50ff8 */
/* Reserved 0x51028 - 0x517f8 */
#define PEC_CORE_AND_BLOCK_INTERRUPT_STATUS_OE 0
/* Reserved 0x51810 - 0x51ff8 */
#define ILU_DEVICE_CAPABILITIES_ESTAR 0
/* cru.csr CRU module defines */
#define DMC_DEBUG_SELECT_FOR_PORT_A_SIGNAL_SEL 0
#define DMC_DEBUG_SELECT_FOR_PORT_B_SIGNAL_SEL 0
/* Reserved 0x53010 - 0x530f8 */
#define DMC_PCI_EXPRESS_CONFIGURATION_REQ_ID 0
/* psb.csr PSB module defines */
#define PACKET_SCOREBOARD_DMA_SET_ENTRIES_ENTRY 0
/* Reserved 0x60100 - 0x63ff8 */
#define PACKET_SCOREBOARD_PIO_SET_ENTRIES_ENTRY 0
/* tsb.csr TSB module defines */
#define TRANSACTION_SCOREBOARD_SET_ENTRIES_ENTRY 0
#define TRANSACTION_SCOREBOARD_STATUS_EMPTY 0
/* tlr.csr TLR module defines */
#define TLU_CONTROL_CONFIG 0
#define TLU_STATUS_STATUS 0
#define TLU_PME_TURN_OFF_GENERATE_PTO 0
#define TLU_INGRESS_CREDITS_INITIAL_PDC 0
/* Reserved 0x80020 - 0x800f8 */
#define TLU_DIAGNOSTIC_IFC_DIS 0
/* Reserved 0x80108 - 0x801f8 */
#define TLU_EGRESS_CREDITS_CONSUMED_PDC 0
#define TLU_EGRESS_CREDIT_LIMIT_PDC 0
#define TLU_EGRESS_RETRY_BUFFER_CL 0
#define TLU_INGRESS_CREDITS_ALLOCATED_PDC 0
#define TLU_INGRESS_CREDITS_RECEIVED_PDC 0
/* Reserved 0x80228 - 0x80ff8 */
#define TLU_OTHER_EVENT_LOG_ENABLE_EN 0
#define TLU_OTHER_EVENT_INTERRUPT_ENABLE_EN_P 0
#define TLU_OTHER_EVENT_INTERRUPT_STATUS_ERR_P 0
#define TLU_OTHER_EVENT_STATUS_CLEAR_EIP_P 0
#define TLU_OTHER_EVENT_STATUS_SET_EIP_P 0
#define TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG_HDR 0
#define TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG_HDR 0
#define TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG_HDR 0
#define TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG_HDR 0
/* Reserved 0x81048 - 0x81ff8 */
#define TLU_PERFORMANCE_COUNTER_SELECT_SEL0 0
#define TLU_PERFORMANCE_COUNTER_ZERO_CNT 0
#define TLU_PERFORMANCE_COUNTER_ONE_CNT 0
#define TLU_PERFORMANCE_COUNTER_TWO_CNT 0
/* Reserved 0x82020 - 0x82ff8 */
#define TLU_DEBUG_SELECT_A_SIGNAL 0
#define TLU_DEBUG_SELECT_B_SIGNAL 0
/* Reserved 0x83010 - 0x8fff8 */
#define TLU_DEVICE_CAPABILITIES_MPS 0
#define TLU_LINK_CAPABILITIES_SPEED 0
#define TLU_LINK_CONTROL_ASPM 0
#define TLU_LINK_STATUS_SPEED 0
/* Reserved 0x90038 - 0x90ff8 */
#define TLU_UNCORRECTABLE_ERROR_LOG_ENABLE_EN 0
#define TLU_UNCORRECTABLE_INTERRUPT_STATUS_TE_P 0
#define TLU_UNCORRECTABLE_ERROR_STATUS_SET_TE_P 0
0xffffffffffffffff
0xffffffffffffffff
0xffffffffffffffff
0xffffffffffffffff
/* Reserved 0x91048 - 0x9fff8 */
/* Reserved 0xa0008 - 0xa0ff8 */
#define TLU_CORRECTABLE_ERROR_LOG_ENABLE_EN 0
#define TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RE_P 0
#define TLU_CORRECTABLE_ERROR_STATUS_SET_RE_P 0
/* lpr.csr LPR module defines */
/* Reserved 0xe0008 - 0xe1ff8 */
#define LPU_ID_GBID 0
#define LPU_RESET_RSTRXPCS 0
#define LPU_DEBUG_STATUS_DEBUGA 0
#define LPU_DEBUG_CONFIG_DBUGA_SIG_SEL 0
#define LPU_LTSSM_CONTROL_HOT_RESET 0
#define LPU_LINK_STATUS_LINK_SPEED 0
/* Reserved 0xe2030 - 0xe2038 */
#define LPU_INTERRUPT_STATUS_INT_PHY_GB 0
#define LPU_INTERRUPT_MASK_MSK_PHY_GB 0
/* Reserved 0xe2050 - 0xe20f8 */
/* Reserved 0xe2108 - 0xe2108 */
/* Reserved 0xe2118 - 0xe2118 */
#define LPU_LINK_PERFORMANCE_COUNTER1_PERF_CNTR1 0
#define LPU_LINK_PERFORMANCE_COUNTER2_PERF_CNTR2 0
/* Reserved 0xe2140 - 0xe21f8 */
#define LPU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS 0
/* Reserved 0xe2228 - 0xe2238 */
/* Reserved 0xe2248 - 0xe2258 */
0x7fff
0x7fff
0x7fff
0x7fff
/* Reserved 0xe2278 - 0xe23f8 */
0xffff
#define LPU_TXLINK_REPLAY_TIMER_RPLAY_TMR 0
#define LPU_TXLINK_TEST_CONTROL_FORCE_RTX_TLP 0
/* Reserved 0xe2478 - 0xe2478 */
/* Reserved 0xe24b0 - 0xe24b8 */
/* Reserved 0xe24d8 - 0xe24d8 */
/* Reserved 0xe24e8 - 0xe24f8 */
0xfff
/* Reserved 0xe2518 - 0xe25f8 */
#define LPU_PHY_INTERRUPT_MASK_MSK_ILL_STP_POS 0
/* Reserved 0xe2628 - 0xe2678 */
#define LPU_RECEIVE_PHY_CONFIG_RST_RCV_LANE 0
#define LPU_RECEIVE_PHY_STATUS1_RX_PHY_STS 0
#define LPU_RECEIVE_PHY_STATUS2_RCV_LINK_NUM 0
#define LPU_RECEIVE_PHY_STATUS3_BYTE_SYNC_STS 0
/* Reserved 0xe26b8 - 0xe26f8 */
#define LPU_TRANSMIT_PHY_CONFIG_FRCE_ELEC_IDLE 0
#define LPU_TRANSMIT_PHY_STATUS_TX_PHY_SMS 0
/* Reserved 0xe2730 - 0xe2778 */
#define LPU_LTSSM_CONFIG1_LTSSM_20_TO 0
#define LPU_LTSSM_CONFIG2_LTSSM_12_TO 0
#define LPU_LTSSM_CONFIG3_LTSSM_2_TO 0
#define LPU_LTSSM_CONFIG4_LNK_NUM 0
#define LPU_LTSSM_CONFIG5_CFG_UNUSED_2 0
#define LPU_LTSSM_STATUS1_CNFG_LNK_WDTH 0
#define LPU_LTSSM_STATUS2_RX_CMD_RX_PHY 0
#define LPU_LTSSM_INTERRUPT_AND_STATUS_INT_NONE 0
#define LPU_LTSSM_INTERRUPT_MASK_MSK_NONE 0
/* Reserved 0xe27d8 - 0xe27f8 */
#define LPU_GIGABLAZE_GLUE_CONFIG2_RX_TERM 0
#define LPU_GIGABLAZE_GLUE_CONFIG3_BIT_LCK_TM 0
#define LPU_GIGABLAZE_GLUE_CONFIG4_INIT_TIME 0
#define LPU_GIGABLAZE_GLUE_STATUS_BIT_SYNC_DN 0
#define LPU_GIGABLAZE_GLUE_POWER_DOWN1_THE 0
#define LPU_GIGABLAZE_GLUE_POWER_DOWN1_RX_PWR_DN 0
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PX_REGS_H */