Lines Matching refs:x7
188 #define JBUS_CHANGE_INITIATION_CONTROL_CDELAY_MASK 0x7
322 #define JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_S_INT_EN_MASK 0x7
353 #define JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_P_INT_EN_MASK 0x7
388 #define JBC_ERROR_LOG_ENABLE_SPARE_LOG_EN_MASK 0x7
420 #define JBC_INTERRUPT_ENABLE_SPARE_S_INT_EN_MASK 0x7
451 #define JBC_INTERRUPT_ENABLE_SPARE_P_INT_EN_MASK 0x7
483 #define JBC_INTERRUPT_STATUS_SPARE_S_MASK 0x7
514 #define JBC_INTERRUPT_STATUS_SPARE_P_MASK 0x7
546 #define JBC_ERROR_STATUS_CLEAR_SPARE_S_MASK 0x7
577 #define JBC_ERROR_STATUS_CLEAR_SPARE_P_MASK 0x7
777 #define FIRE_AND_JBC_DEBUG_SELECT_A_BLOCK_SEL_MASK 0x7
779 #define FIRE_AND_JBC_DEBUG_SELECT_A_SUB_SEL_MASK 0x7
781 #define FIRE_AND_JBC_DEBUG_SELECT_A_SIGNAL_SEL_MASK 0x7
786 #define FIRE_AND_JBC_DEBUG_SELECT_B_BLOCK_SEL_MASK 0x7
788 #define FIRE_AND_JBC_DEBUG_SELECT_B_SUB_SEL_MASK 0x7
790 #define FIRE_AND_JBC_DEBUG_SELECT_B_SIGNAL_SEL_MASK 0x7
873 #define EVENT_QUEUE_STATE_ENTRIES_STATE_MASK 0x7
1152 #define MMU_CONTROL_AND_STATUS_ROE_MASK 0x7
1422 #define DMC_DEBUG_SELECT_FOR_PORT_A_SUB_SEL_MASK 0x7
1424 #define DMC_DEBUG_SELECT_FOR_PORT_A_SIGNAL_SEL_MASK 0x7
1429 #define DMC_DEBUG_SELECT_FOR_PORT_B_SUB_SEL_MASK 0x7
1431 #define DMC_DEBUG_SELECT_FOR_PORT_B_SIGNAL_SEL_MASK 0x7
1477 #define TLU_CONTROL_CTO_SEL_MASK 0x7
1735 #define TLU_DEBUG_SELECT_A_BLOCK_MASK 0x7
1737 #define TLU_DEBUG_SELECT_A_MODULE_MASK 0x7
1739 #define TLU_DEBUG_SELECT_A_SIGNAL_MASK 0x7
1742 #define TLU_DEBUG_SELECT_B_BLOCK_MASK 0x7
1744 #define TLU_DEBUG_SELECT_B_MODULE_MASK 0x7
1746 #define TLU_DEBUG_SELECT_B_SIGNAL_MASK 0x7
1752 #define TLU_DEVICE_CAPABILITIES_L1_MASK 0x7
1754 #define TLU_DEVICE_CAPABILITIES_L0S_MASK 0x7
1756 #define TLU_DEVICE_CAPABILITIES_MPS_MASK 0x7
1759 #define TLU_DEVICE_CONTROL_MRRS_MASK 0x7
1761 #define TLU_DEVICE_CONTROL_MPS_MASK 0x7
1768 #define TLU_LINK_CAPABILITIES_L1_MASK 0x7
1770 #define TLU_LINK_CAPABILITIES_L0S_MASK 0x7
1956 #define LPU_RESET_RSTUNUSED_MASK 0x7
2066 #define LPU_LINK_LAYER_CONFIG_UNUSED_MASK 0x7
2078 #define LPU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK 0x7
2295 #define LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_POST_VAL_MASK 0x7
2298 #define LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_PREAM_VAL_MASK 0x7
2588 #define LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_ADJUST_MASK 0x7
2599 #define LPU_GIGABLAZE_GLUE_CONFIG2_TX_RISE_FALL_MASK 0x7
2601 #define LPU_GIGABLAZE_GLUE_CONFIG2_TX_PRE_EMPH_MASK 0x7
2628 #define LPU_GIGABLAZE_GLUE_CONFIG3_TX_PLL_FDBK_DIV_MASK 0x7
2631 #define LPU_GIGABLAZE_GLUE_CONFIG3_RX_PLL_FDBK_DIV_MASK 0x7