Searched defs:level (Results 1 - 6 of 6) sorted by relevance

/solaris-x11-s11/open-src/lib/libXext/sun-src/src/
H A DFBPM.c154 req->level = state;
179 CARD16 level)
186 if ((level != FBPMModeOn) &&
187 (level != FBPMModeStandby) &&
188 (level != FBPMModeSuspend) &&
189 (level != FBPMModeOff))
196 req->level = level;
177 FBPMForceLevel( Display *dpy, CARD16 level) argument
/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_panel.c436 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) argument
440 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
443 static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level) argument
448 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
449 level = intel_panel_compute_brightness(dev, level);
452 intel_pch_panel_set_backlight(dev, level);
464 lbpc = level * 0xfe / max + 1;
465 level /= lbpc;
471 level <<
477 intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max) argument
[all...]
H A Di915_gem_gtt.c57 enum i915_cache_level level)
62 switch (level) {
84 enum i915_cache_level level)
94 if (level != I915_CACHE_NONE)
102 enum i915_cache_level level)
107 if (level != I915_CACHE_NONE)
480 * Binds an object into the global gtt with the specified cache level. The object
486 enum i915_cache_level level)
503 dev_priv->gtt.pte_encode(dev, page_addr, level));
519 dev_priv->gtt.pte_encode(dev, page_addr, level));
55 gen6_pte_encode(struct drm_device *dev, uint64_t addr, enum i915_cache_level level) argument
82 byt_pte_encode(struct drm_device *dev, uint64_t addr, enum i915_cache_level level) argument
100 hsw_pte_encode(struct drm_device *dev, uint64_t addr, enum i915_cache_level level) argument
485 gen6_ggtt_insert_entries(struct drm_i915_gem_object *obj, enum i915_cache_level level) argument
[all...]
H A Di915_gem.c2796 DRM_DEBUG("can not change the cache level of pinned objects\n");
2879 enum i915_cache_level level; local
2884 level = I915_CACHE_NONE;
2887 level = I915_CACHE_LLC;
2903 ret = i915_gem_object_set_cache_level(obj, level);
H A Dintel_pm.c1029 * intel_calculate_wm - calculate watermark level
1035 * Calculate the watermark level (the level at which the display plane will
1041 * on the pixel size. When it reaches the watermark level, it'll start
1068 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1696 static bool ironlake_check_srwm(struct drm_device *dev, int level, argument
1704 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1708 fbc_wm, SNB_FBC_MAX_SRWM, level);
1722 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1728 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1743 ironlake_compute_srwm(struct drm_device *dev, int level, int plane, int latency_ns, const struct intel_watermark_params *display, const struct intel_watermark_params *cursor, int *fbc_wm, int *display_wm, int *cursor_wm) argument
2441 int level, max_level, wm_lp; local
[all...]
H A Di915_drv.h486 enum i915_cache_level level);
511 enum i915_cache_level level);
1092 int level; member in struct:drm_i915_private::__anon157

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