Searched refs:dpll (Results 1 - 5 of 5) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_display.c420 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) argument
422 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp) argument
3079 if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3115 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3120 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
4295 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) argument
4300 i9xx_dpll_compute_fp(struct dpll *dpll) argument
4411 u32 dpll, mdiv; local
4506 I915_WRITE(DPLL(pipe), dpll); local
4532 u32 dpll; local
4604 I915_WRITE(DPLL(pipe), dpll); local
4620 I915_WRITE(DPLL(pipe), dpll); local
4632 u32 dpll; local
4665 I915_WRITE(DPLL(pipe), dpll); local
4676 I915_WRITE(DPLL(pipe), dpll); local
5608 ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) argument
5621 uint32_t dpll; local
5709 u32 dpll = 0, fp = 0, fp2 = 0; local
6947 u32 dpll = I915_READ(DPLL(pipe)); local
7069 int dpll; local
7112 int dpll; local
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H A Dintel_dp.c644 pipe_config->dpll.p1 = 2;
645 pipe_config->dpll.p2 = 10;
646 pipe_config->dpll.n = 2;
647 pipe_config->dpll.m1 = 23;
648 pipe_config->dpll.m2 = 8;
650 pipe_config->dpll.p1 = 1;
651 pipe_config->dpll.p2 = 10;
652 pipe_config->dpll.n = 1;
653 pipe_config->dpll.m1 = 14;
654 pipe_config->dpll
[all...]
H A Dintel_drv.h166 typedef struct dpll { struct
234 /* Settings for the intel dpll used on pretty much everything but
236 struct dpll dpll; member in struct:intel_crtc_config
238 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
241 /* Actual register state of the dpll, for shared dpll cross-checking. */
248 * Frequence the dpll for the port should run at. Differs from the
H A Di915_drv.h136 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
137 /* real shared dpll ids must be >= 0 */
144 uint32_t dpll; member in struct:intel_dpll_hw_state
341 struct dpll;
365 struct dpll *match_clock,
366 struct dpll *best_clock);
H A Dintel_sdvo.c1057 struct dpll *clock = &pipe_config->dpll;
1261 /* done in crtc_mode_set as it lives inside the dpll register */
1345 * the sdvo port register, on all other platforms it is part of the dpll

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