Searched refs:t1_write_reg_4 (Results 1 - 15 of 15) sorted by relevance

/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dtp.c64 t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size);
65 t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base);
66 t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base);
67 t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size);
68 t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size);
69 t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs);
70 t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size);
71 t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs);
79 t1_write_reg_4(adapter, A_TP_CM_SIZE, cm_size);
80 t1_write_reg_4(adapte
[all...]
H A Despi.c54 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
59 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
77 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
82 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
106 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST);
122 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST);
139 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
140 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
146 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
147 t1_write_reg_4(esp
[all...]
H A Dulp.c49 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, ULP_INTR_MASK);
50 t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
58 t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP);
59 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff);
68 t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
70 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, 0);
115 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, cause);
135 t1_write_reg_4(adapter, A_ULP_HREG_INDEX, i);
136 t1_write_reg_4(adapter, A_ULP_HREG_DATA, 0);
139 t1_write_reg_4(adapte
[all...]
H A Dcspi.c38 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0xffffffff);
44 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0);
53 /* t1_write_reg_4( adapter, CSPI_REG_RAMSTATUS, ); */
62 t1_write_reg_4(adapter, A_CSPI_CALENDAR_LEN, 15);
63 t1_write_reg_4(adapter, A_CSPI_FIFO_STATUS_ENABLE, 1);
H A Dmc3.c51 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
52 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3);
55 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE,
57 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
68 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, 0);
69 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
73 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, 0);
74 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
91 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE,
93 t1_write_reg_4(mc
[all...]
H A Dmc4.c68 t1_write_reg_4(adapter, addr, val);
92 t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP);
103 t1_write_reg_4(adapter, A_MC4_STROBE,
116 t1_write_reg_4(adapter, A_MC4_STROBE,
159 t1_write_reg_4(adapter, A_MC4_REFRESH,
163 t1_write_reg_4(adapter, A_MC4_ECC_CNTL,
167 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0);
168 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1);
169 t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0);
170 t1_write_reg_4(adapte
[all...]
H A Dmc5.c129 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_CMD, cmd);
143 t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base);
163 t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base);
182 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, v1);
183 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR1, v2);
184 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR2, v3);
189 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA0, v1);
190 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA1, v2);
191 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA2, v3);
208 t1_write_reg_4(adapte
[all...]
H A Dch_mac.c94 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr);
99 t1_write_reg_4(mac->adapter,
120 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr);
125 t1_write_reg_4(mac->adapter,
144 t1_write_reg_4(mac->adapter, A_PL_CAUSE,
150 t1_write_reg_4(mac->adapter,
182 t1_write_reg_4(mac->adapter, MAC_REG_CSR(idx),
211 t1_write_reg_4(mac->adapter,
248 t1_write_reg_4(mac->adapter,
263 t1_write_reg_4(ma
[all...]
H A Dch_subr.c90 t1_write_reg_4(adapter, A_TPI_ADDR, addr);
91 t1_write_reg_4(adapter, A_TPI_WR_DATA, value);
92 t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR);
121 t1_write_reg_4(adapter, A_TPI_ADDR, addr);
122 t1_write_reg_4(adapter, A_TPI_CSR, 0);
151 t1_write_reg_4(adapter, A_TPI_PAR, V_TPIPAR(value));
217 t1_write_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE, cause);
247 t1_write_reg_4(adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,
259 t1_write_reg_4(adapter, A_PL_CAUSE, cause);
270 t1_write_reg_4(adapte
[all...]
H A Dpm3393.c169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr);
251 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr);
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dsge.c125 t1_write_reg_4(sge->obj, A_SG_DOORBELL, control_reg);
264 t1_write_reg_4(sge->obj, A_SG_CONTROL, sge->sge_control);
284 t1_write_reg_4(sge->obj, A_SG_CONTROL, 0x0);
290 t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, status);
509 t1_write_reg_4(sge->obj, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK);
510 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, 0);
526 t1_write_reg_4(sge->obj, A_PL_ENABLE, val | SGE_PL_INTR_MASK);
530 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, en);
540 t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK);
541 t1_write_reg_4(sg
[all...]
H A Dglue.c96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) function
244 t1_write_reg_4(chp, pe->addr, pe->pe_reg_val);
H A Dch.h286 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
H A Dpe.c1519 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT);
1521 t1_write_reg_4(adapter, A_PL_ENABLE, enable | F_PL_INTR_EXT);
1534 t1_write_reg_4(adapter, A_PL_ENABLE, enable & ~F_PL_INTR_EXT);
1598 t1_write_reg_4(adapter, MTUREG(i), mtu);
H A Dch.c768 t1_write_reg_4(chp->sge->obj, A_SG_CONTROL, 0x0);
769 t1_write_reg_4(chp->sge->obj, A_SG_INT_CAUSE, 0x0);

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