d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * t1_wait_op_done - wait until an operation is completed
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @adapter: the adapter performing the operation
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @reg: the register to check for completion
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @mask: a single-bit field within @reg that indicates completion
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @polarity: the value of the field when the operation is completed
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @attempts: number of check iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @delay: delay in usecs between iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @attempts: number of check iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @delay: delay in usecs between iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Wait until an operation is completed by checking a bit in a register
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * up to @attempts times. Returns %0 if the operation completes and %1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * otherwise.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (--attempts == 0)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* #define TPI_ATTEMPTS 50 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Write a register over the TPI interface (unlocked and locked versions).
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read a register over the TPI interface (unlocked and locked versions).
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Set a TPI parameter.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Called when a port's link settings change to propagate the new values to the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * associated PHY and MAC. After performing the common tasks it invokes an
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * OS-specific handler.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct link_config *lc = &adapter->port[port_id].link_config;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set MAC speed, duplex, and flow control to match PHY. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * PHY interrupt handler for FPGA boards.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause = t1_read_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Slow path interrupt handler for FPGAs.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA doesn't support MC4 interrupts and it requires
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * this odd layer of indirection for MC5.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear TP interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear the interrupts just processed. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (cause != 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA MDIO initialization.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void fpga_mdio_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA MDIO read/write operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check if MDI is busy; this shouldn't happen. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EBUSY);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check if MDI is busy; this shouldn't happen. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EBUSY);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Wait until Elmer's MI1 interface is ready for new operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * MI1 MDIO initialization.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Elmer MI1 MDIO read/write operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_readinc(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the operation we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Read the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the operation we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Read the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T110 1x10GBase-CX4 TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio N110 1x10GBaseX NIC" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio N210 1x10GBaseX NIC" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T210 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T210 1x10GBase-CX4 TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_IXF1010, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 100000000/*clk-core*/, 133000000/*clk-mc3*/, 100000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T204 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 100000000/*clk-core*/, 133000000/*clk-mc3*/, 100000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T204V 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_TP /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 16000000/*clk-core*/, 16000000/*clk-mc3*/, 16000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*espi-ports*/, 0/*clk-cspi*/, 0/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_chelsio_mac_ops, &t1_mv88e1xxx_ops, &fpga_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio FPGA 4x10/100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_TP /*caps*/, CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 7500 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 7500 4x1000BaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_TP | SUPPORTED_PAUSE | SUPPORTED_LOOPBACK /*caps*/, CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 83300000/*clk-core*/, 83300000/*clk-mc3*/, 83300000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 2/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T101 1x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE | SUPPORTED_PAUSE | SUPPORTED_LOOPBACK /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 83300000/*clk-core*/, 83300000/*clk-mc3*/, 83300000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 2/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T101 1x1000BaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 8000 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T110 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_TP /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 333300000/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_vsc7321_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio Cougar 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 333300000/*clk-cspi*/, 40/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_vsc7321_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio Cougar 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 125000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 0/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 0/*mdc*/, 0/*phybaseaddr*/, &t1_dummy_mac_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_dummy_phy_ops, NULL, "Chelsio simulation environment TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Return the board_info structure with a given index. Out-of-range indices
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * return NULL.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (board_id < DIMOF(t1_board) ? &t1_board[board_id] : NULL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Return the board_info structure that corresponds to a given PCI devid/ssid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * pair. Return NULL if the id combination is unknown.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *t1_get_board_info_from_ids(unsigned int devid,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short ssid)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u8 pad[2]; /* make multiple-of-4 size requirement explicit */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read SEEPROM. A zero is written to the flag register when the addres is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * written to the Control register. The hardware device will set the flag to a
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * one when 4B have been transferred to the Data register.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_2(adapter, A_PCICFG_VPD_ADDR, (u16)addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EIO);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_VPD_DATA, data);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int t1_eeprom_vpd_get(adapter_t *adapter, chelsio_vpd_t *vpd)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (addr = 0; !ret && addr < sizeof (*vpd); addr += sizeof (u32))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read a port's MAC address from the VPD ROM.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Set up the MAC/PHY according to the requested link settings.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If the PHY can auto-negotiate first decide what to advertise, then
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * enable/disable auto-negotiation as desired and reset.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If the PHY does not auto-negotiate we just reset it.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * otherwise do it later based on the outcome of auto-negotiation.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (fc == ((PAUSE_RX | PAUSE_TX) & !is_T2(mac->adapter)))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Also disables autoneg */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * External interrupt handler for boards using elmer0.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Elmer0's interrupt cause isn't useful here because there is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * only one bit that can be set for all 4 ports. This means
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * we are forced to check every PHY's interrupt status
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * register to see who initiated the interrupt.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Enables all interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask |= F_PL_INTR_MC3 | F_PL_INTR_MC4 |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * T2 -- Disable interrupts for now b/c we are not clearing
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * correctly yet.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* t1_ulp_intr_enable(adapter->ulp); */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable PCIX & external chip interrupts on ASIC boards. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_ENABLE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Disables all interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Disable MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Disable PCIX & external chip interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_ENABLE, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Clears all interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable interrupts for external devices. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Slow path interrupt handler for ASICs.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear the interrupts just processed. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Power sequencing is a work-around for Intel's XPAKs. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check for XPAK */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* XPAK is present */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Enable board components other than the Chelsio chip, such as external MAC
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and PHY.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int board_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * TBD XXX Might not need. This fixes a problem
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * described in the Intel SR XPAK errata.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Initialize and configure the Terminator HW modules. Note that external
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * MAC and PHYs are initialized separately.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc3 && t1_mc3_init(adapter->mc3, bi->clock_mc3))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4 && t1_mc4_init(adapter->mc4, bi->clock_mc4))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY | F_MC4_SLOW);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw err = t1_sge_configure(adapter->sge, &adapter->params.sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Determine a card's PCI mode.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw static unsigned short speed_map[] = { 33, 66, 100, 133 };
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_MODE, &pci_mode);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Release the structures holding the SW per-Terminator-HW-module state.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void __devinit init_link_config(struct link_config *lc,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Allocate and initialize the data structures that hold the SW state of
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * the Terminator HW modules.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.stats_update_period = bi->gmac->stats_update_period;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Must wait 200us after power up before touching the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * memory controllers.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.tp.pm_size = t1_mc3_get_size(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.tp.cm_size = t1_mc4_get_size(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.nservers = DEFAULT_SERVER_REGION_LEN;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Get the port's MAC addresses either from the EEPROM if one
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * exists or the one hardcoded in the MAC.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);