d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * or http://www.opensolaris.org/os/licensing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#pragma ident "%Z%%M% %I% %E% SMI" /* ch_subr.c */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "common.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "elmer0.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "regs.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "gmac.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "cphy.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "sge.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "tp.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "espi.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "mc3.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "mc4.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "mc5.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "ulp.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "cspi.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * t1_wait_op_done - wait until an operation is completed
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @adapter: the adapter performing the operation
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @reg: the register to check for completion
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @mask: a single-bit field within @reg that indicates completion
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @polarity: the value of the field when the operation is completed
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @attempts: number of check iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @delay: delay in usecs between iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @attempts: number of check iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @delay: delay in usecs between iterations
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Wait until an operation is completed by checking a bit in a register
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * up to @attempts times. Returns %0 if the operation completes and %1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * otherwise.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int attempts, int delay)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw while (attempts) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val = t1_read_reg_4(adapter, reg) & mask;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!!val == polarity)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (--attempts == 0)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (delay)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw DELAY_US(delay);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* #define TPI_ATTEMPTS 50 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TPI_ATTEMPTS 100
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Write a register over the TPI interface (unlocked and locked versions).
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw__t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int tpi_busy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_WR_DATA, value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_ATTEMPTS, 3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (tpi_busy)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ALERT("%s: TPI write to 0x%x failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter), addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (tpi_busy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int ret;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ret = __t1_tpi_write(adapter, addr, value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (ret);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read a register over the TPI interface (unlocked and locked versions).
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw__t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int tpi_busy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_CSR, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_ATTEMPTS, 3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (tpi_busy)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ALERT("%s: TPI read from 0x%x failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter), addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *valp = t1_read_reg_4(adapter, A_TPI_RD_DATA);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (tpi_busy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int ret;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ret = __t1_tpi_read(adapter, addr, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (ret);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Set a TPI parameter.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void t1_tpi_par(adapter_t *adapter, u32 value)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_TPI_PAR, V_TPIPAR(value));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Called when a port's link settings change to propagate the new values to the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * associated PHY and MAC. After performing the common tasks it invokes an
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * OS-specific handler.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwlink_changed(adapter_t *adapter, int port_id)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int link_ok, speed, duplex, fc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cphy *phy = adapter->port[port_id].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct link_config *lc = &adapter->port[port_id].link_config;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->speed = speed < 0 ? SPEED_INVALID : speed;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(lc->requested_fc & PAUSE_AUTONEG))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set MAC speed, duplex, and flow control to match PHY. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cmac *mac = adapter->port[port_id].mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->fc = (unsigned char)fc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int t1_pci_intr_handler(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pcix_cause;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &pcix_cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (pcix_cause) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pcix_cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_fatal_err(adapter); /* PCI errors are fatal */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "fpga_defs.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * PHY interrupt handler for FPGA boards.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_phy_intr_handler(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int p;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause = t1_read_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, p)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & (1 << p)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cphy *phy = adapter->port[p].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, p);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Slow path interrupt handler for FPGAs.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_slow_intr(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw cause &= ~F_PL_INTR_SGE_DATA;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_SGE_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_intr_error_handler(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & FPGA_PCIX_INTERRUPT_GMAC)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) fpga_phy_intr_handler(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & FPGA_PCIX_INTERRUPT_TP) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA doesn't support MC4 interrupts and it requires
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * this odd layer of indirection for MC5.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 tp_cause = t1_read_reg_4(adapter,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw FPGA_TP_ADDR_INTERRUPT_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (tp_cause & FPGA_TP_INTERRUPT_MC5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc5_intr_handler(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear TP interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw tp_cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & FPGA_PCIX_INTERRUPT_MC3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_mc3_intr_handler(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & FPGA_PCIX_INTERRUPT_PCIX)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_pci_intr_handler(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear the interrupts just processed. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_PL_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (cause != 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA MDIO initialization.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void fpga_mdio_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) bi; /* avoid warnings */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MI0_CLK, V_MI0_CLK_DIV(3));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA MDIO read/write operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int *val)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mmd_addr)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check if MDI is busy; this shouldn't happen. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ALERT("%s: MDIO busy at start of read\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EBUSY);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MI0_ADDR,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *val = t1_read_reg_4(adapter, A_MI0_DATA_EXT);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int val)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mmd_addr)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check if MDI is busy; this shouldn't happen. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ALERT("%s: MDIO busy at start of write\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EBUSY);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MI0_ADDR,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MI0_DATA_EXT, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic struct mdio_ops fpga_mdio_ops = {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw fpga_mdio_init,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw fpga_mdio_read,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw fpga_mdio_write
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Wait until Elmer's MI1 interface is ready for new operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int attempts = 100, busy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw do {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, mi1_reg, &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw busy = val & F_MI1_OP_BUSY;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (busy)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw DELAY_US(10);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } while (busy && --attempts);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (busy)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ALERT("%s: MDIO operation timed out\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (busy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * MI1 MDIO initialization.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(bi->caps & SUPPORTED_10000baseT_Full))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw val |= V_MI1_SOF(1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Elmer MI1 MDIO read/write operations.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int *valp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mmd_addr)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_DIRECT_READ);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int val)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mmd_addr)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_DIRECT_WRITE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic struct mdio_ops mi1_mdio_ops = {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_init,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_read,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_write
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_readinc(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int *valp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_ADDRESS);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the operation we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_READ_INC);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Read the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int *valp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_ADDRESS);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the operation we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_READ);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Read the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int reg_addr, unsigned int val)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_LOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the address we want. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_ADDRESS);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Write the data. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MI1_OP_INDIRECT_WRITE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TPI_UNLOCK(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic struct mdio_ops mi1_mdio_ext_ops = {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_init,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_ext_read,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mi1_mdio_ext_write
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T110_1CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_N110_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_N210_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T210_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T210_1CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T204_4CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T204V_4CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_6800_4CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_7500_4CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_7500_4F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T101_1CU_LB,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T101_1F_LB,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_8000_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_T110_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_COUGAR_4CU,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_COUGAR_1F,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_USERMODE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_BRD_SIMUL,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic struct board_info t1_board[] = {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT110, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_MY3126,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_my3126_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T110 1x10GBase-CX4 TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_N110, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_88X2010,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio N110 1x10GBaseX NIC" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_N210, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_88X2010,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio N210 1x10GBaseX NIC" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT210, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_88X2010,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T210 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT210, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_MY3126,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_my3126_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T210 1x10GBase-CX4 TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT204, 4/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_IXF1010, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 100000000/*clk-core*/, 133000000/*clk-mc3*/, 100000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T204 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT204V, 4/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 100000000/*clk-core*/, 133000000/*clk-mc3*/, 100000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T204V 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_6800, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_TP /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_FPGA, CHBT_MAC_CHELSIO_A, CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 16000000/*clk-core*/, 16000000/*clk-mc3*/, 16000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*espi-ports*/, 0/*clk-cspi*/, 0/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_chelsio_mac_ops, &t1_mv88e1xxx_ops, &fpga_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio FPGA 4x10/100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_7500, 4/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_TP /*caps*/, CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 7500 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_7500, 4/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 7500 4x1000BaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT101, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_TP | SUPPORTED_PAUSE | SUPPORTED_LOOPBACK /*caps*/, CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 83300000/*clk-core*/, 83300000/*clk-mc3*/, 83300000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 2/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T101 1x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT101, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE | SUPPORTED_PAUSE | SUPPORTED_LOOPBACK /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T1, CHBT_MAC_IXF1010, CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 83300000/*clk-core*/, 83300000/*clk-mc3*/, 83300000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 2/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 4/*phybaseaddr*/, &t1_ixf1010_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T101 1x1000BaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_8000, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_XPAK,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 40/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_xpak_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio 8000 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_CHT110, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393, CHBT_PHY_XPAK,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_xpak_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio T110 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_COUGAR, 4/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_TP /*caps*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T1, CHBT_MAC_VSC7321, CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 4/*espi-ports*/, 333300000/*clk-cspi*/, 40/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 4/*mdc*/, 0/*phybaseaddr*/, &t1_vsc7321_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_mv88e1xxx_ops, &mi1_mdio_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio Cougar 4x100/1000BaseT TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_COUGAR, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_VSC7321, CHBT_PHY_XPAK,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 87500000/*clk-core*/, 87500000/*clk-mc3*/, 87500000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 333300000/*clk-cspi*/, 40/*clk-elmer0*/, 1/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_vsc7321_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_xpak_ops, &mi1_mdio_ext_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw "Chelsio Cougar 1x10GBaseX TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_USERMODE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{ CHBT_BOARD_SIMUL, 1/*ports#*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*caps*/, CHBT_TERM_T1, CHBT_MAC_DUMMY, CHBT_PHY_DUMMY,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 125000000/*clk-core*/, 125000000/*clk-mc3*/, 125000000/*clk-mc4*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 1/*espi-ports*/, 0/*clk-cspi*/, 0/*clk-elmer0*/, 0/*mdien*/,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0/*mdiinv*/, 0/*mdc*/, 0/*phybaseaddr*/, &t1_dummy_mac_ops,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &t1_dummy_phy_ops, NULL, "Chelsio simulation environment TOE" },
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct pci_device_id t1_pci_tbl[] = {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(8, 0, CH_BRD_T110_1CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(8, 1, CH_BRD_T110_1CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(7, 0, CH_BRD_N110_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(10, 1, CH_BRD_N210_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(11, 1, CH_BRD_T210_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(14, 1, CH_BRD_T210_1CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(12, 1, CH_BRD_T204_4CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(13, 1, CH_BRD_T204V_4CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(1, 0, CH_BRD_6800_4CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(2, 1, CH_BRD_7500_4CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(2, 3, CH_BRD_7500_4F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(4, 0, CH_BRD_T101_1CU_LB),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(4, 2, CH_BRD_T101_1F_LB),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(3, 0, CH_BRD_8000_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(3, 1, CH_BRD_8000_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(6, 0, CH_BRD_T110_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(6, 1, CH_BRD_T110_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(5, 0, CH_BRD_COUGAR_4CU),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(5, 1, CH_BRD_COUGAR_1F),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_USERMODE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DEVICE(0x5000, PCI_ANY_ID, CH_BRD_SIMUL),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw { 0, }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifndef CH_DEVICE_COMMON
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Return the board_info structure with a given index. Out-of-range indices
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * return NULL.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_get_board_info(unsigned int board_id)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (board_id < DIMOF(t1_board) ? &t1_board[board_id] : NULL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#else
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Return the board_info structure that corresponds to a given PCI devid/ssid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * pair. Return NULL if the id combination is unknown.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *t1_get_board_info_from_ids(unsigned int devid,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short ssid)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pci_device_id *p;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (p = t1_pci_tbl; p->devid; ++p)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (p->devid == devid && p->ssid == ssid)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (&t1_board[p->board_info_index]);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (NULL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 format_version;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u8 serial_number[16];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u8 mac_base_address[6];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u8 pad[2]; /* make multiple-of-4 size requirement explicit */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} chelsio_vpd_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define EEPROMSIZE (8 * 1024)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define EEPROM_MAX_POLL 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read SEEPROM. A zero is written to the flag register when the addres is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * written to the Control register. The hardware device will set the flag to a
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * one when 4B have been transferred to the Data register.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int i = EEPROM_MAX_POLL;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u16 val;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (addr >= EEPROMSIZE || (addr & 3))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EINVAL);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_2(adapter, A_PCICFG_VPD_ADDR, (u16)addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw do {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw DELAY_US(50);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_2(adapter,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw A_PCICFG_VPD_ADDR, &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } while (!(val & F_VPD_OP_FLAG) && --i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(val & F_VPD_OP_FLAG)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: reading EEPROM address 0x%x failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter), addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-EIO);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_VPD_DATA, data);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *data = le32_to_cpu(*data);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int t1_eeprom_vpd_get(adapter_t *adapter, chelsio_vpd_t *vpd)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int addr, ret = 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (addr = 0; !ret && addr < sizeof (*vpd); addr += sizeof (u32))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ret = t1_seeprom_read(adapter, addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (u32 *)((u8 *)vpd + addr));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (ret);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read a port's MAC address from the VPD ROM.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw chelsio_vpd_t vpd;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_eeprom_vpd_get(adapter, &vpd))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw memcpy(mac_addr, vpd.mac_base_address, 5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac_addr[5] = vpd.mac_base_address[5] + index;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Set up the MAC/PHY according to the requested link settings.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If the PHY can auto-negotiate first decide what to advertise, then
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * enable/disable auto-negotiation as desired and reset.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If the PHY does not auto-negotiate we just reset it.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * otherwise do it later based on the outcome of auto-negotiation.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (lc->supported & SUPPORTED_Autoneg) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (fc) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (fc == ((PAUSE_RX | PAUSE_TX) & !is_T2(mac->adapter)))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising |= ADVERTISED_PAUSE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising |= ADVERTISED_ASYM_PAUSE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (fc == PAUSE_RX)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising |= ADVERTISED_PAUSE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->advertise(phy, lc->advertising);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (lc->autoneg == AUTONEG_DISABLE) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->speed = lc->requested_speed;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->duplex = lc->requested_duplex;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->fc = (unsigned char)fc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->set_speed_duplex_fc(mac, lc->speed,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->duplex, fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Also disables autoneg */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->state = PHY_AUTONEG_RDY;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->reset(phy, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } else {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->state = PHY_AUTONEG_EN;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->autoneg_enable(phy); /* also resets PHY */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } else {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->state = PHY_AUTONEG_RDY;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->fc = (unsigned char)fc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->reset(phy, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * External interrupt handler for boards using elmer0.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwelmer0_ext_intr_handler(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cphy *phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int phy_cause;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw switch (board_info(adapter)->board) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT204:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT204V: {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int i, port_bit;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port_bit = i ? i + 1 : 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(cause & (1 << port_bit))) continue;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy = adapter->port[i].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT101:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy = adapter->port[0].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_7500: {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int p;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Elmer0's interrupt cause isn't useful here because there is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * only one bit that can be set for all 4 ports. This means
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * we are forced to check every PHY's interrupt status
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * register to see who initiated the interrupt.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, p) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy = adapter->port[p].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, p);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT210:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_N210:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_N110:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy = adapter->port[0].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_8000:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT110:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cmac *mac = adapter->port[0].mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->interrupt_handler(mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 mod_detect;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, A_ELMER0_GPI_STAT,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw &mod_detect);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mod_detect ? "removed" : "inserted");
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_COUGAR:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->params.nports == 1) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT1) { /* Vitesse MAC */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cmac *mac = adapter->port[0].mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->interrupt_handler(mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } else {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int i, port_bit;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port_bit = i ? i + 1 : 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(cause & (1 << port_bit))) continue;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy = adapter->port[i].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy_cause = phy->ops->interrupt_handler(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy_cause & cphy_cause_link_change)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw link_changed(adapter, i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Enables all interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_interrupts_enable(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_intr_enable(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tp_intr_enable(adapter->tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask |= F_PL_INTR_MC3 | F_PL_INTR_MC4 |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_PL_INTR_ULP | F_PL_INTR_MC5;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * T2 -- Disable interrupts for now b/c we are not clearing
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * correctly yet.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* t1_ulp_intr_enable(adapter->ulp); */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_ulp_intr_disable(adapter->ulp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc3_intr_enable(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc4_intr_enable(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc5_intr_enable(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask |= F_PL_INTR_ESPI;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_espi_intr_enable(adapter->espi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].mac->ops->interrupt_enable(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].phy->ops->interrupt_enable(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable PCIX & external chip interrupts on ASIC boards. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pl_intr = t1_read_reg_4(adapter, A_PL_ENABLE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_ENABLE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_PL_ENABLE, pl_intr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Disables all interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_interrupts_disable(adapter_t * adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_intr_disable(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tp_intr_disable(adapter->tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_ulp_intr_disable(adapter->ulp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc3_intr_disable(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc4_intr_disable(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc5_intr_disable(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_espi_intr_disable(adapter->espi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Disable MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].mac->ops->interrupt_disable(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].phy->ops->interrupt_disable(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Disable PCIX & external chip interrupts. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(adapter))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_PL_ENABLE, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_ENABLE, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->slow_intr_mask = 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Clears all interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_interrupts_clear(adapter_t * adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_intr_clear(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tp_intr_clear(adapter->tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_ulp_intr_clear(adapter->ulp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc3_intr_clear(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc4_intr_clear(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc5_intr_clear(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_espi_intr_clear(adapter->espi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear MAC/PHY interrupts for each port. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].mac->ops->interrupt_clear(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].phy->ops->interrupt_clear(adapter->
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port[i].phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Enable interrupts for external devices. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_PL_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* PCI-X interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_write_config_4(adapter, A_PCICFG_INTR_CAUSE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Slow path interrupt handler for ASICs.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int asic_slow_intr(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw cause &= adapter->slow_intr_mask;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!cause)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_SGE_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_intr_error_handler(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_TP)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tp_intr_handler(adapter->tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_MC3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_mc3_intr_handler(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_MC4)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_mc4_intr_handler(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_ULP)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_ulp_intr_handler(adapter->ulp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_MC5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_mc5_intr_handler(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_ESPI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_espi_intr_handler(adapter->espi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_PCIX)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_pci_intr_handler(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PL_INTR_EXT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_elmer0_ext_intr(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear the interrupts just processed. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_PL_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_slow_intr_handler(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!t1_is_asic(adapter))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (fpga_slow_intr(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (asic_slow_intr(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Power sequencing is a work-around for Intel's XPAKs. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwpower_sequence_xpak(adapter_t * adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 mod_detect;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 gpo;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Check for XPAK */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!(ELMER0_GP_BIT5 & mod_detect)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* XPAK is present */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw gpo |= ELMER0_GP_BIT18;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct adapter_params *p)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->chip_version = bi->chip_term;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (p->chip_version == CHBT_TERM_T1 ||
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->chip_version == CHBT_TERM_T2 ||
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->chip_version == CHBT_TERM_FPGA) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val = t1_read_reg_4(adapter, A_TP_PC_CONFIG);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw val = G_TP_PC_REV(val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (val == 2)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->chip_revision = TERM_T1B;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else if (val == 3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->chip_revision = TERM_T2;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } else
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Enable board components other than the Chelsio chip, such as external MAC
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and PHY.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int board_init(adapter_t *adapter, const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw switch (bi->board) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_8000:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_N110:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_N210:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT210:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_COUGAR:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tpi_par(adapter, 0xf);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT110:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tpi_par(adapter, 0xf);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * TBD XXX Might not need. This fixes a problem
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * described in the Intel SR XPAK errata.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw power_sequence_xpak(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_1G
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT204:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT204V:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tpi_par(adapter, 0xf);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_CHT101:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw case CHBT_BOARD_7500:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tpi_par(adapter, 0xf);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw break;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Initialize and configure the Terminator HW modules. Note that external
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * MAC and PHYs are initialized separately.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_init_hw_modules(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int err = -EIO;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw const struct board_info *bi = board_info(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc3 && t1_mc3_init(adapter->mc3, bi->clock_mc3))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4 && t1_mc4_init(adapter->mc4, bi->clock_mc4))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc5 && t1_mc5_init(adapter->mc5,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.nservers,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.nroutes, 1, 0))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->ulp && t1_ulp_init(adapter->ulp,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.tp.pm_tx_base))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 val = t1_read_reg_4(adapter, A_MC4_CFG);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY | F_MC4_SLOW);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_MC5_CONFIG,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_M_BUS_ENABLE | F_TCAM_RESET);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->cspi && t1_cspi_init(adapter->cspi))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw bi->espi_nports))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw err = t1_sge_configure(adapter->sge, &adapter->params.sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (err)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto out_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tp_set_coalescing_size(adapter->tp,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw min(adapter->params.sge.large_buf_capacity,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TP_MAX_RX_COALESCING_SIZE));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw err = 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwout_err:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (err);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Determine a card's PCI mode.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw static unsigned short speed_map[] = { 33, 66, 100, 133 };
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pci_mode;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_os_pci_read_config_4(adapter, A_PCICFG_MODE, &pci_mode);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Release the structures holding the SW per-Terminator-HW-module state.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwt1_free_sw_modules(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cmac *mac = adapter->port[i].mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cphy *phy = adapter->port[i].phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mac)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->destroy(mac);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (phy)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw phy->ops->destroy(phy);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->sge)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_sge_destroy(adapter->sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->tp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_tp_destroy(adapter->tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->espi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_espi_destroy(adapter->espi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc5_destroy(adapter->mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc3_destroy(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->mc4)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_mc4_destroy(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_ulp_destroy(adapter->ulp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (adapter->cspi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_cspi_destroy(adapter->cspi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic void __devinit init_link_config(struct link_config *lc,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->supported = bi->caps;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->requested_speed = lc->speed = SPEED_INVALID;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (lc->supported & SUPPORTED_Autoneg) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising = lc->supported;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->autoneg = AUTONEG_ENABLE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->requested_fc |= PAUSE_AUTONEG;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw } else {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->advertising = 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw lc->autoneg = AUTONEG_DISABLE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid init_mtus(unsigned short mtus[])
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[0] = 68;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[1] = 508;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[2] = 576;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[3] = 1492;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[4] = 1500;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[5] = 2000;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[6] = 4000;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mtus[7] = 9000;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Allocate and initialize the data structures that hold the SW state of
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * the Terminator HW modules.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint __devinit t1_init_sw_modules(adapter_t *adapter,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw const struct board_info *bi)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.brd_info = bi;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.nports = bi->port_number;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.stats_update_period = bi->gmac->stats_update_period;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->sge) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: SGE initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->clock_mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Must wait 200us after power up before touching the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * memory controllers.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw DELAY_US(200);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->mc3 = t1_mc3_create(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->mc3) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: MC3 initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->mc4 = t1_mc4_create(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->mc4) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: MC4 initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->params.mc5.mode)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.mode = MC5_MODE_144_BIT;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->mc5 = t1_mc5_create(adapter,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.mode);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->mc5) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: MC5 initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->ulp = t1_ulp_create(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->ulp) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: ULP initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.tp.pm_size = t1_mc3_get_size(adapter->mc3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.tp.cm_size = t1_mc4_get_size(adapter->mc4);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.nservers = DEFAULT_SERVER_REGION_LEN;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.mc5.nroutes = DEFAULT_RT_REGION_LEN;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw init_mtus(adapter->params.mtus);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_COUGAR
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: CSPI initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: ESPI initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->tp) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: TP initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) board_init(adapter, bi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw bi->mdio_ops->init(adapter, bi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->gphy->reset)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw bi->gphy->reset(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (bi->gmac->reset)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw bi->gmac->reset(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for_each_port(adapter, i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u8 hw_addr[6];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct cmac *mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int phy_addr = bi->mdio_phybaseaddr + i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw bi->mdio_ops);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!adapter->port[i].phy) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: PHY %d initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter), i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!mac) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: MAC %d initialization failed\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_name(adapter), i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Get the port's MAC addresses either from the EEPROM if one
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * exists or the one hardcoded in the MAC.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac->ops->macaddress_get(mac, hw_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else if (vpd_macaddress_get(adapter, i, hw_addr)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: could not read MAC address from VPD ROM\n",
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw port_name(adapter, i));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw goto error;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_set_hw_addr(adapter, i, hw_addr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw init_link_config(&adapter->port[i].link_config, bi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw get_pci_mode(adapter, &adapter->params.pci);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_interrupts_clear(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwerror:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_free_sw_modules(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return (-1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}