/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* mc5.c */
#include "common.h"
#include "regs.h"
#include "mc5.h"
/* DBGI command mode */
enum {
};
/* Lara command register address and values (low 32 bits) */
/* Lara config register address and values (low 32 bits) */
/* Lara GMR base addresses (low 32 bits) */
/* Lara 7000 data and mask array base addresses (low 32 bits) */
/* Lara commands */
/* IDT 75P52100 commands */
/* IDT LAR register address and value for 144-bit mode (low 32 bits) */
/* IDT SCR and SSR addresses (low 32 bits) */
/* IDT GMR base address (low 32 bits) */
/* IDT data and mask array base addresses (low 32 bits) */
enum {
};
static unsigned int tcam_part_size[] = {
4718592, /* 4.5Mb */
9437184, /* 9Mb */
18874368 /* 18Mb */
};
struct pemc5 {
unsigned int tcam_size;
unsigned int part_size;
unsigned char part_type;
unsigned char parity_enabled;
unsigned char issue_syn;
unsigned char mode;
#ifdef SUPPORT_MODE72
unsigned int lip_index;
#endif
};
/*
* Issue a command to the TCAM and wait for its completion. The address and
* any data required by the command must have been setup by the caller.
*/
{
}
{
}
{
return 0;
}
{
}
{
return tcam_size - tcam_rtable_base;
}
{
return 0;
}
{
}
{
return tcam_rtable_base - tcam_server_base;
}
{
}
{
}
{
}
/*
* Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
* command cmd. The data to be written must have been set up by the caller.
* Returns -1 on failure, 0 on success.
*/
{
return 0;
CH_ERR("%s: MC5 timeout writing to TCAM address 0x%x\n",
return -1;
}
{
unsigned int i;
/*
* We need the size of the TCAM data and mask arrays in terms of
* 72-bit entries.
*/
/* Clear the data array */
dbgi_wr_data3(adap, 0, 0, 0);
for (i = 0; i < size72; i++)
return -1;
/* Initialize the mask array. */
for (i = 0; i < size72; i++) {
if (i == server_base) /* entering server or routing region */
0xfffffff9 : 0xfffffffd);
return -1;
}
return 0;
}
{
int i;
if (mc5->parity_enabled) {
}
/* Set DBGI command mode for Lara TCAM. */
0, 0);
goto err;
0, 0);
goto err;
/* Global Mask Registers (GMR) 0-15 */
for (i = 0; i < 16; i++) {
if (i == 8 || i == 9)
0xfffffffd : 0xfffffff9, 0xffffffff,
0xff);
else
goto err;
}
/* Global Mask Registers (GMR) 16-31 */
for (i = 0; i < 16; i++) {
else if (i == 0)
else if (i == 1)
else
goto err;
}
err:
return -EIO;
}
{
int i;
/*
* Use GMRs 8-9 for ACK and AOPEN searches, GMRs 12-13 for SYN search,
* and GMRs 14-15 for ELOOKUP.
*/
/* Set DBGI command mode for IDT TCAM. */
/* Set up LAR */
goto err;
/* Set up SSRs */
goto err;
/* Set up GMRs */
for (i = 0; i < 32; ++i) {
if (i >= 12 && i < 15)
else if (i == 15)
else
goto err;
}
/* Set up SCR */
goto err;
err:
return -EIO;
}
/* Put MC5 in DBGI mode. */
{
}
/* Put MC5 in M-Bus mode. */
{
}
/*
* Initialization that requires the OS and protocol layers to already
* be intialized goes here.
*/
{
int err = 0;
/* Reset the TCAM */
return -1;
}
return -EINVAL;
#ifdef SUPPORT_MODE72
#endif
/* All the TCAM addresses we access have only the low 32 bits non 0 */
case LARA_7000:
break;
case IDT75P52100:
break;
default:
break;
}
return err;
}
/*
* read_mc5_range - dump a part of the memory managed by MC5
* @mc5: the MC5 handle
* @start: the start address for the dump
* @n: number of 72-bit words to read
* @buf: result buffer
*
* Read n 72-bit words from MC5 memory from the given start location.
*/
{
/* int err = 0; */
else
return -EINVAL;
while (n--) {
/* err = -EIO; */
break;
}
buf += 3;
}
return 0;
}
{
if (!mc5->parity_enabled)
mask &= ~F_MC5_INT_PARITY_ERR;
#ifdef CONFIG_CHELSIO_T1_1G
/*
* Enable child block for MC5.
*
* NOTE: Assumes TP parent interrupt block is enabled.
* MC5 requires TP parent block to be enabled.
*/
} else
#endif
{
pl_intr | F_PL_INTR_MC5);
}
}
{
#ifdef CONFIG_CHELSIO_T1_1G
else
#endif
{
pl_intr & ~F_PL_INTR_MC5);
}
}
{
#ifdef CONFIG_CHELSIO_T1_1G
} else
#endif
{
}
}
/*
* We don't really do anything with MC5 interrupts, just record them.
*/
{
if (cause & F_MC5_INT_MISS_ERR)
if (cause & F_MC5_INT_LIP0_ERR)
if (cause & F_MC5_INT_LIP_MISS_ERR)
}
if (cause & F_MC5_INT_NFA_SRCH_ERR)
if (cause & F_MC5_INT_SYN_COOKIE)
if (cause & F_MC5_INT_SYN_COOKIE_BAD)
if (cause & F_MC5_INT_SYN_COOKIE_OFF)
if (cause & F_MC5_INT_UNKNOWN_CMD)
if (cause & F_MC5_INT_REQUESTQ_PARITY_ERR) {
CH_ALERT("%s: MC5 request queue parity error\n",
adapter_name(adap));
}
if (cause & F_MC5_INT_DISPATCHQ_PARITY_ERR) {
CH_ALERT("%s: MC5 dispatch queue parity error\n",
adapter_name(adap));
}
if (cause & F_MC5_INT_DEL_ACT_EMPTY)
if (cause & MC5_INT_FATAL)
}
{
return &mc5->intr_counts;
}
{
return NULL;
if (cfg & F_TCAM_PART_TYPE_HI)
/*
* Calculate the size of the TCAM based on the total memory, mode, and
* count information retrieved from the hardware.
*/
return mc5;
}
{
}
#ifdef SUPPORT_MODE72
{
return -1;
}
/*
* DESC: Write local IP addresses to the TCAM
*
* NOTES: IP addresses should be in host byte order. So, an IP address:
* of 10.0.0.140 == (data = 0x0A00008C)
*/
int num_of_lip_addresses)
{
int i;
/*
* Disable compression and M bus mode so that the TP core
* doesn't access the TCAM while we are writing.
*/
/* MC5 should now be ready to program the LIP addresses. */
for (i = 0; i < num_of_lip_addresses; i++) {
}
/* Restore MC5 mode. */
return 0;
}
/*
* The purpose of this routine is to write all of the local IP addresses
* into the TCAM in sorted order. This is a requirement from the TCAM.
*/
{
int i;
}
}
{
}
/*
* Add a local IP address to the LIP table.
*/
{
return 0;
}
#endif