d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * or http://www.opensolaris.org/os/licensing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Use is subject to license terms.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * This file is part of the Chelsio T1 Ethernet driver.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifndef _CHELSIO_CH_H
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define _CHELSIO_CH_H
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#pragma ident "%Z%%M% %I% %E% SMI"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include <sys/debug.h>
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef __cplusplus
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwextern "C" {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Definitions for module_info
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHIDNUM (666) /* module ID number */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHNAME "chxge" /* module name */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHMINPSZ (0) /* min packet size */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHMAXPSZ ETHERMTU /* max packet size */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHHIWAT (32 * 1024) /* hi-water mark */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHLOWAT (1) /* lo-water mark */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_NO_HWCKSUM 0x1 /* hardware should no add checksum */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_NO_CPL 0x2 /* no cpl header with data */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_OFFLOAD 0x4 /* do TCP/IP offload processing */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_ARP 0x8 /* dummy arp packet (don't free) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_TCP_MF 0x10 /* Indicator of Fragmented TCP */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_UDP_MF 0x20 /* Indicator of Fragmented UDP */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CH_UDP 0x40 /* Indicator of regular TCP */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define SZ_INUSE 64 /* # of in use counters */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * PCI registers
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define BAR0 1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define BAR1 2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define BAR2 3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define BAR3 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * TOE pre-mapped buffer structure
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct tbuf {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct tbuf *tb_next; /* next entry in free list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw caddr_t tb_base; /* base of buffer */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint64_t tb_pa; /* physical address of buffer */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t tb_dh; /* dma handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t tb_ah; /* dma address handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw void *tb_sa; /* address of card ctrl struct */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t tb_debug; /* initally 0 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t tb_len; /* length of data */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} tbuf_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif /* CONFIG_CHELSIO_T1_OFFLOAD */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * header structures to hold pre-mapped (DMA) kernel memory buffers.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct ch_esb {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct ch_esb *cs_next; /* next entry in list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct ch_esb *cs_owner; /* list of buffers owned by ch_t */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw void *cs_sa; /* card structure to get ch ptr */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t cs_dh; /* dma handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t cs_ah; /* dma address handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw caddr_t cs_buf; /* vaddr of buffer */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint64_t cs_pa; /* paddr of buffer */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t cs_index; /* index of buffer_in_use count */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t cs_flag; /* if set, commit suicide */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef FRAGMENT /* we assume no fragments */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ddi_dma_cookie_t cs_cookie[MAXFS];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t cs_ncookie;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw frtn_t cs_frtn; /* for esballoc */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} ch_esb_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * structure for linked list of multicast addresses that have been
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * assigned to the card.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct ch_mc {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct ch_mc *cmc_next;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint8_t cmc_mca[6];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} ch_mc_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * structure for linked list of pre-allocated dma handles for command Q
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct free_dh {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct free_dh *dhe_next;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t dhe_dh;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} free_dh_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * instance configuration
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct ch_cfg {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t cksum_enabled: 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t burstsize_set: 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t burstsize: 2;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t transaction_cnt_set: 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t transaction_cnt: 3;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t relaxed_ordering: 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t enable_dvma: 1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} ch_cfg_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Per-card state information
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwtypedef struct ch {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw dev_info_t *ch_dip; /* device dev info */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw gld_mac_info_t *ch_macp; /* gld mac structure */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_cfg_t ch_config; /* instance configuration */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t ch_flags; /* state flags */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t ch_state; /* card state */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t ch_blked; /* card is blked on output */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_lock; /* lock for ch structure */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw caddr_t ch_pci; /* PCI configuration vaddr */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ddi_acc_handle_t ch_hpci; /* PCI configuration access handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw off_t ch_pcisz; /* size of PCI configuration space */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw caddr_t ch_bar0; /* PCI BAR0 vaddr */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ddi_acc_handle_t ch_hbar0; /* PCI BAR0 access handle */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw off_t ch_bar0sz; /* size of BAR0 space */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ddi_iblock_cookie_t ch_icookp; /* hardware interrupt cookie ptr */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_intr; /* lock for interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_maximum_mtu; /* maximum mtu for adapter */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_sm_buf_sz; /* size of sm esballoc bufs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_sm_buf_aln; /* alignment of sm esballoc bufs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_esb_t *ch_small_esb_free; /* free list sm esballoc bufs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_esb_t *ch_small_owner; /* list small bufs owned by ch_t */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_small_esbl; /* lock for ch_small_esb list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t ch_sm_index; /* small buffer in use count index */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_bg_buf_sz; /* size of bg esballoc bufs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_bg_buf_aln; /* alignment of bg esballoc bufs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_esb_t *ch_big_esb_free; /* free list of esballoc entries */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_esb_t *ch_big_owner; /* list big bufs owned by ch_t */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_big_esbl; /* lock for ch_esb list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint_t ch_big_index; /* big buffer in use count index */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_mc_lck; /* lock of mulitcast list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ch_mc_t *ch_mc; /* list of multicast entries */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_mc_cnt; /* cnt of multicast entries */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* XXX see how we can use cmdQ_ce list and get rid of lock */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t ch_dh_lck; /* lock for ch_dh list */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw free_dh_t *ch_dh; /* list of free dma headers for v2p */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(__sparc)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* XXX see how we can use cmdQ_ce list and get rid of lock */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw free_dh_t *ch_vdh; /* list of free dvma headers for v2p */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_ip; /* ip address from first arp */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_mtu; /* size of device MTU (1500 default) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* XXX config_data needs cleanup */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pe_config_data_t config_data; /* card configuration vector */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pe_port_t port[4]; /* from freebsd/oschtoe.h driver */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pesge *sge;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pemc3 *mc3;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pemc4 *mc4;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pemc5 *mc5;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct petp *tp;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pecspi *cspi;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct peespi *espi;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct peulp *ulp;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t open_device_map;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct adapter_params params;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint16_t vendor_id;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint16_t device_id;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint16_t device_subid;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint16_t chip_revision;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint16_t chip_version;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t is_asic;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t config;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t ch_unit;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint8_t init_counter;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw char *ch_name;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* statistics per card */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t isr_intr; /* # interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t oerr; /* send error (no mem) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t norcvbuf;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int ch_refcnt;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw void *ch_toeinst;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw void (*toe_rcv)(void *, mblk_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw void (*toe_free)(void *, tbuf_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int (*toe_tunnel)(void *, mblk_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kcondvar_t *ch_tx_overflow_cv;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t *ch_tx_overflow_mutex;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t slow_intr_mask;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef HOST_PAUSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t txxg_cfg1; /* Place holder for MAC cfg reg1. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int pause_on;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw hrtime_t pause_time;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw kmutex_t mac_lock; /* lock for MAC structure */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw} ch_t;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* ch_flags */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PEIDLE 0x00 /* chip is uninitialized */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PERUNNING 0x01 /* chip is initialized */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PEPROMISC 0x04 /* promiscuous mode enabled */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PEALLMULTI 0x08 /* all multicast enabled */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PESUSPENDED 0x20 /* suspended interface */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PENORES 0x40 /* ran out of xmit resources */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PESTOP 0x80 /* gldm_stop done */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PEINITDONE 0x100 /* initialization done */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TSO_CAPABLE 0x200 /* TSO able */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* open_device_map flag */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TOEDEV_DEVMAP_BIT 0x1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * DMA mapping defines
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DMA_STREAM 1 /* use DDI_DMA_STREAMING for DMA xfers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DMA_4KALN 2 /* align memory to 4K page boundry */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DMA_OUT 4 /* this is a write buffer */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DMA_SMALN 8 /* aligned at small buffer boundry */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DMA_BGALN 16 /* aligned at big buffer boundry */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Number of multicast addresses per stream
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHMAXMC 64
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHMCALLOC (CHMAXMC * sizeof (struct ether_addr))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* ----- Solaris memory - PCI - DMA mapping functions ------ */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid *ch_alloc_dma_mem(ch_t *, int, int, int, uint64_t *, ulong_t *, ulong_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid ch_free_dma_mem(ulong_t, ulong_t);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid ch_unbind_dma_handle(ch_t *, free_dh_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid ch_send_up(ch_t *, mblk_t *, uint32_t, int);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid ch_gld_ok(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwuint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwuint32_t t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwuint32_t t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwuint32_t le32_to_cpu(uint32_t data);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid *t1_os_malloc_wait_zero(size_t len);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_os_free(void *adr, size_t len);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_num_of_ports(ch_t *obj);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint pe_os_mem_copy(ch_t *obj, void *dst, void *src, size_t len);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid *pe_os_malloc_contig_wait_zero(ch_t *, size_t, uint64_t *,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t *, ulong_t *, uint32_t);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_set_mac(ch_t *sa, unsigned char *ac_enaddr);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwunsigned char *pe_get_mac(ch_t *sa);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_set_promiscuous(ch_t *sa, int flag);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint pe_get_stats(ch_t *sa, uint64_t *speed, uint32_t *intrcnt,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t *norcvbuf, uint32_t *oerrors, uint32_t *ierrors,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t *underrun, uint32_t *overrun, uint32_t *framing,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t *crc, uint32_t *carrier, uint32_t *collisions,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t *xcollisions, uint32_t *late, uint32_t *defer,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw uint32_t *xerrs, uint32_t *rerrs, uint32_t *toolong, uint32_t *runt,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t *multixmt, ulong_t *multircv, ulong_t *brdcstxmt,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulong_t *brdcstrcv);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint pe_attach(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_detach(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_init(void *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwuint_t pe_intr(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef CONFIG_CHELSIO_T1_OFFLOAD
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define toe_running(a) (a->open_device_map & TOEDEV_DEVMAP_BIT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint pe_start(ch_t *sa, mblk_t *mb, uint32_t flg);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_stop(ch_t *sa);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_ioctl(ch_t *, queue_t *, mblk_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint pe_set_mc(ch_t *, uint8_t *, int);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint tpi_read(ch_t *obj, u32 addr, u32 *value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid CH_ALERT(const char *fmt, ...);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid CH_WARN(const char *fmt, ...);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid CH_ERR(const char *fmt, ...);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_fatal_err(ch_t *chp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define memset(s, c, n) bzero(s, n)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwextern int enable_checksum_offload;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_dma_handle_init(ch_t *, int);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwfree_dh_t *ch_get_dma_handle(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_free_fake_arp(void *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid pe_mark_freelists(ch_t *chp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#if defined(__sparc)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwfree_dh_t *ch_get_dvma_handle(ch_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid ch_unbind_dvma_handle(ch_t *, free_dh_t *);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define AMD_VENDOR_ID 0x1022
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define AMD_BRIDGE 0x7450
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define AMD_BRIDGE_REV 0x12
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifdef __cplusplus
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif /* _CHELSIO_CH_H */