d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* DBGI command mode */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Lara command register address and values (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Lara config register address and values (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Lara GMR base addresses (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Lara 7000 data and mask array base addresses (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Lara commands */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IDT 75P52100 commands */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IDT LAR register address and value for 144-bit mode (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IDT SCR and SSR addresses (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IDT GMR base address (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IDT data and mask array base addresses (low 32 bits) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Issue a command to the TCAM and wait for its completion. The address and
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * any data required by the command must have been setup by the caller.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int set_tcam_rtbl_base(struct pemc5 *mc5, unsigned int rtbl_base)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int tcam_rtable_base = t1_mc5_get_tcam_rtbl_base(mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int set_tcam_server_base(struct pemc5 *mc5, unsigned int server_base)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwunsigned int t1_mc5_get_tcam_server_base(struct pemc5 *mc5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwunsigned int t1_mc5_get_tcam_server_size(struct pemc5 *mc5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int tcam_rtable_base = t1_mc5_get_tcam_rtbl_base(mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int tcam_server_base = t1_mc5_get_tcam_server_base(mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * command cmd. The data to be written must have been set up by the caller.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Returns -1 on failure, 0 on success.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int init_mask_data_array(struct pemc5 *mc5, u32 mask_array_base,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * We need the size of the TCAM data and mask arrays in terms of
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * 72-bit entries.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int size72 = tcam_part_size[mc5->part_size] / 72;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int server_base = t1_mc5_get_tcam_server_base(mc5);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw server_base *= 2; /* 1 144-bit entry is 2 72-bit entries */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear the data array */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < size72; i++)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Initialize the mask array. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < size72; i++) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (i == server_base) /* entering server or routing region */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set DBGI command mode for Lara TCAM. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_LARA_7000);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MC5_LRA_CMDREG_144KEY_DATA0 : MC5_LRA_CMDREG_72KEY_DATA0,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mc5_write(adap, MC5_LRA_CMDREG_ADR0, MC5_LRA_CMD_WRITE))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw MC5_LRA_CFGREG_144KEY_DATA0 : MC5_LRA_CFGREG_72KEY_DATA0,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mc5_write(adap, MC5_LRA_CFGREG_ADR0, MC5_LRA_CMD_WRITE))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Global Mask Registers (GMR) 0-15 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < 16; i++) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Global Mask Registers (GMR) 16-31 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < 16; i++) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else if (i == 0)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else if (i == 1)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return init_mask_data_array(mc5, MC5_LRA_MSKARY_BASE_ADR0,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Use GMRs 8-9 for ACK and AOPEN searches, GMRs 12-13 for SYN search,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and GMRs 14-15 for ELOOKUP.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_POPEN_DATA_WR_CMD, MC5_IDT_CMD_WRITE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_POPEN_MASK_WR_CMD, MC5_IDT_CMD_WRITE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_AOPEN_SRCH_CMD, MC5_IDT_CMD_SEARCH);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_AOPEN_LRN_CMD, MC5_IDT_CMD_LEARN);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_SYN_SRCH_CMD, MC5_IDT_CMD_SEARCH | 0x6000);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_SYN_LRN_CMD, MC5_IDT_CMD_LEARN);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_ACK_SRCH_CMD, MC5_IDT_CMD_SEARCH);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_ACK_LRN_CMD, MC5_IDT_CMD_LEARN);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_ILOOKUP_CMD, MC5_IDT_CMD_SEARCH);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_ELOOKUP_CMD, MC5_IDT_CMD_SEARCH | 0x7000);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_DATA_WRITE_CMD, MC5_IDT_CMD_WRITE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_DATA_READ_CMD, MC5_IDT_CMD_READ);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set DBGI command mode for IDT TCAM. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_IDT_52100);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set up LAR */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mc5_write(adap, MC5_IDT_LAR_ADR0, MC5_IDT_CMD_WRITE))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set up SSRs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mc5_write(adap, MC5_IDT_SSR0_ADR0, MC5_IDT_CMD_WRITE) ||
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set up GMRs */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < 32; ++i) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else if (i == 15)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Set up SCR */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (mc5_write(adap, MC5_IDT_SCR_ADR0, MC5_IDT_CMD_WRITE))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return init_mask_data_array(mc5, MC5_IDT_MSKARY_BASE_ADR0,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Put MC5 in DBGI mode. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline void mc5_dbgi_mode_enable(struct pemc5 *mc5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Put MC5 in M-Bus mode. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Initialization that requires the OS and protocol layers to already
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * be intialized goes here.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Reset the TCAM */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw cfg |= V_MODE(mc5->mode == MC5_MODE_72_BIT) | F_TCAM_RESET;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_wait_op_done(adap, A_MC5_CONFIG, F_TCAM_READY, 1, 500, 0)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: TCAM reset timed out\n", adapter_name(adap));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw set_tcam_server_base(mc5, tcam_size - nroutes - nservers))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* All the TCAM addresses we access have only the low 32 bits non 0 */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CH_ERR("%s: unsupported TCAM type\n", adapter_name(adap));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * read_mc5_range - dump a part of the memory managed by MC5
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @mc5: the MC5 handle
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @start: the start address for the dump
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @n: number of 72-bit words to read
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * @buf: result buffer
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read n 72-bit words from MC5 memory from the given start location.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_read_mc5_range(struct pemc5 *mc5, unsigned int start,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* int err = 0; */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw while (n--) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* err = -EIO; */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MC5_INT_MASK (F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_MC5_INT_ACTIVE_REGION_FULL | F_MC5_INT_NFA_SRCH_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MC5_INT_FATAL (F_MC5_INT_PARITY_ERR | F_MC5_INT_REQUESTQ_PARITY_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Enable child block for MC5.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * NOTE: Assumes TP parent interrupt block is enabled.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * MC5 requires TP parent block to be enabled.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * We don't really do anything with MC5 interrupts, just record them.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if ((cause & F_MC5_INT_PARITY_ERR) && mc5->parity_enabled) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct pemc5_intr_counts *t1_mc5_get_intr_counts(struct pemc5 *mc5)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct pemc5 * __devinit t1_mc5_create(adapter_t *adapter, int mode)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Calculate the size of the TCAM based on the total memory, mode, and
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * count information retrieved from the hardware.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mc5->tcam_size = tcam_part_size[mc5->part_size] / bits_per_entry;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * DESC: Write local IP addresses to the TCAM
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * NOTES: IP addresses should be in host byte order. So, an IP address:
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * of 10.0.0.140 == (data = 0x0A00008C)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Disable compression and M bus mode so that the TP core
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * doesn't access the TCAM while we are writing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* MC5 should now be ready to program the LIP addresses. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < num_of_lip_addresses; i++) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_LIP_RAM_ADDR, 0x100 + i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Restore MC5 mode. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(mc5->adapter, A_MC5_CONFIG, cfg | F_COMPRESSION_ENABLE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The purpose of this routine is to write all of the local IP addresses
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * into the TCAM in sorted order. This is a requirement from the TCAM.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = mc5->lip_index; i < MC5_LIP_NUM_OF_ENTRIES; i++)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mc5_set_lip_entries(mc5, mc5->lip, MC5_LIP_NUM_OF_ENTRIES);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Add a local IP address to the LIP table.