d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * or http://www.opensolaris.org/os/licensing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#pragma ident "%Z%%M% %I% %E% SMI" /* ulp.c */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "common.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "regs.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "ulp.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct peulp {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_t *adapter;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct ulp_intr_counts intr_counts;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define ULP_INTR_MASK (F_HREG_PAR_ERR | F_EGRS_DATA_PAR_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_INGRS_DATA_PAR_ERR | F_PM_INTR | F_PM_E2C_SYNC_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_PM_C2E_SYNC_ERR | F_PM_E2C_EMPTY_ERR | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_PM_C2E_EMPTY_ERR | V_PM_PAR_ERR(M_PM_PAR_ERR) | \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw F_PM_E2C_WRT_FULL | F_PM_C2E_WRT_FULL)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_ulp_intr_enable(struct peulp *ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Only ASIC boards support PL_ULP block. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(ulp->adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, ULP_INTR_MASK);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pl_intr | F_PL_INTR_ULP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_ulp_intr_clear(struct peulp *ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(ulp->adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_ulp_intr_disable(struct peulp *ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (t1_is_asic(ulp->adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw pl_intr & ~F_PL_INTR_ULP);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_ulp_intr_handler(struct peulp *ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw u32 cause = t1_read_reg_4(ulp->adapter, A_ULP_INT_CAUSE);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_HREG_PAR_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.region_table_parity_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_EGRS_DATA_PAR_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.egress_tp2ulp_data_parity_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_INGRS_DATA_PAR_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.ingress_tp2ulp_data_parity_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_INTR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_intr++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_E2C_SYNC_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_e2c_cmd_payload_sync_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_C2E_SYNC_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_c2e_cmd_payload_sync_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_E2C_EMPTY_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_e2c_fifo_read_empty_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_C2E_EMPTY_ERR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_c2e_fifo_read_empty_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (G_PM_PAR_ERR(cause))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_parity_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_E2C_WRT_FULL)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_e2c_fifo_write_full_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & F_PM_C2E_WRT_FULL)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->intr_counts.pm_c2e_fifo_write_full_err++;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (cause & ULP_INTR_MASK)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_fatal_err(ulp->adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Clear status */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, cause);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_ulp_init(struct peulp *ulp, unsigned int pm_tx_base)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int i;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter_t *adapter = ulp->adapter;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Initialize ULP Region Table.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The region table memory has read enable tied to one, so data is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * read out every cycle. The address to this memory is not defined
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * at reset and gets set first time when first ulp pdu is handled.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * So after reset an undefined location is accessed, and since it is
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * read before any meaningful data is written to it there can be a
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * parity error.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (i = 0; i < 256; i++) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_HREG_INDEX, i);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_HREG_DATA, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_ULIMIT, pm_tx_base);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_TAGMASK, (pm_tx_base << 1) - 1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!t1_is_T1B(adapter)) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* region table is not used */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_HREG_INDEX, 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* enable page size in pagepod */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_write_reg_4(adapter, A_ULP_PIO_CTRL, 1);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw }
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return 0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct peulp *t1_ulp_create(adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct peulp *ulp = t1_os_malloc_wait_zero(sizeof(*ulp));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw ulp->adapter = adapter;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return ulp;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_ulp_destroy(struct peulp * ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_free((void *)ulp, sizeof(*ulp));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct ulp_intr_counts *t1_ulp_get_intr_counts(struct peulp *ulp)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return &ulp->intr_counts;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}