/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* This file is part of the Chelsio T1 Ethernet driver.
*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* mc4.c */
#include "common.h"
#include "regs.h"
#include "mc4.h"
struct pemc4 {
unsigned int size;
};
{
}
/* Calculate amount of MC4 memory. */
{
!!(mc4_cfg & F_MC4_NARROW);
}
/*
* Write a value to a register and check that the write completed. These
* writes normally complete in a cycle or two, so one read should suffice but
* just in case we give them a bit of grace period. Note that the very first
* read exists to flush the posted write to the device.
*/
{
while (attempts--) {
return 0;
if (attempts)
DELAY_US(1);
}
CH_ERR("%s: write to MC4 register 0x%x timed out\n",
return -EIO;
}
{
int attempts;
/* Power up the FCRAMs. */
/* If we're not in slow mode, we are using the DLLs */
if (!slow_mode) {
/* Clear Reset */
val & ~F_SLAVE_DLL_RESET);
/* Wait for slave DLLs to lock */
}
} else {
/* Initializes the master DLL and slave delay lines. */
val & ~F_MASTER_DLL_RESET);
/* Wait for the master DLL to lock. */
attempts = 100;
do {
DELAY_US(1);
if (!(val & MC4_DLL_DONE)) {
CH_ERR("%s: MC4 DLL lock failed\n",
goto out_fail;
}
}
}
/* Set the FCRAM output drive strength and enable DLLs if needed */
goto out_fail;
/* Specify the FCRAM operating parameters */
goto out_fail;
/* Initiate an immediate refresh and wait for the write to complete. */
goto out_fail;
/* 2nd immediate refresh as before */
goto out_fail;
/* Convert to KHz first to avoid 64-bit division. */
/* Enable periodic refresh. */
/* Use the BIST engine to clear all of the MC4 memory. */
attempts = 100;
do {
DELAY_MS(100);
goto out_fail;
}
/* Enable normal memory accesses. */
return 0;
return -1;
}
{
if (mc4) {
}
return mc4;
}
{
}
{
pl_intr | F_PL_INTR_MC4);
}
}
{
pl_intr & ~F_PL_INTR_MC4);
}
}
{
}
}
{
if (cause & F_MC4_CORR_ERR) {
CH_WARN("%s: MC4 correctable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
}
if (cause & F_MC4_UNCORR_ERR) {
CH_ALERT("%s: MC4 uncorrectable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
}
if (cause & F_MC4_ADDR_ERR) {
}
if (cause & MC4_INT_FATAL)
return 0;
}
{
}
/*
* Read n 256-bit words from MC4 starting at word start, using backdoor
* accesses.
*/
{
return -EINVAL;
return -EIO;
}
if (i == 0) {
i = 8;
buf += 8;
}
}
return 0;
}