/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
H A D | hw_debug.h | 97 val = REG_RD(pdev, MISC_REG_CHIP_NUM); \ 98 chip_rev = REG_RD(pdev, MISC_REG_CHIP_REV); \ 99 chip_metal = REG_RD(pdev, MISC_REG_CHIP_METAL); \ 119 val = REG_RD(pdev, offset); \ 131 val = REG_RD(pdev, offset + i*(inc)); \ 143 val1 = REG_RD(pdev, offset1); \ 144 val2 = REG_RD(pdev, offset2); \ 155 val1 = REG_RD(pdev, (offset1 + i*inc)); \ 156 val2 = REG_RD(pdev, (offset2 + i*(inc))); \ 169 val = REG_RD(pde [all...] |
H A D | lm_er.c | 91 val = REG_RD(pdev, MISC_REG_AEU_GENERAL_MASK); 112 val = REG_RD(pdev, IGU_REG_BLOCK_CONFIGURATION); 224 sr_cnt = REG_RD(pdev, PXP2_REG_RD_SR_CNT); 225 blk_cnt = REG_RD(pdev, PXP2_REG_RD_BLK_CNT); 226 port_is_idle_0 = REG_RD(pdev, PXP2_REG_RD_PORT_IS_IDLE_0); 227 port_is_idle_1 = REG_RD(pdev, PXP2_REG_RD_PORT_IS_IDLE_1); 228 pgl_exp_rom2 = REG_RD(pdev, PXP2_REG_PGL_EXP_ROM2); 229 pgl_b_reg_tags = REG_RD(pdev, PGLUE_B_REG_TAGS_63_32); 269 pend_bits = REG_RD(pdev, IGU_REG_PENDING_BITS_STATUS); 480 val = REG_RD(pde [all...] |
H A D | lm_hw_access.c | 392 val = REG_RD(pdev,MISC_REG_SPIO_INT) ; 397 val = REG_RD(pdev,MISC_REG_SPIO_EVENT_EN) ; 432 swap_val = REG_RD(pdev, NIG_REG_PORT_SWAP); 433 swap_override = REG_RD(pdev, NIG_REG_STRAP_OVERRIDE); 491 reg_val = REG_RD(pdev, MISC_REG_GPIO); 537 swap_val = REG_RD(pdev, NIG_REG_PORT_SWAP); 538 swap_override = REG_RD(pdev, NIG_REG_STRAP_OVERRIDE); 557 gpio_reg = (REG_RD(pdev, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 616 gpio_reg = REG_RD(pdev, MISC_REG_GPIO); 675 swap_val = REG_RD(pde [all...] |
H A D | lm_nvram.c | 72 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); 123 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); 170 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); 212 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); 237 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 259 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 311 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); 314 val=REG_RD(pdev, MCP_REG_MCPR_NVM_READ); 384 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND);
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H A D | lm_hw_init_reset.c | 414 tq_freed_cnt_last = tq_freed_cnt_start = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); 415 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); 423 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); 424 tq_freed_cnt_last = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); 471 inernal_freed_crd_last = inernal_freed_crd_start = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_freed); 472 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); 473 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); 483 credit_last = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); 484 inernal_freed_crd_last = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_freed); 534 tmp = REG_RD(pde [all...] |
H A D | lm_hw_attn.c | 596 val = REG_RD(pdev, MISC_REG_GRC_TIMEOUT_ATTN); 801 nig_status_port = REG_RD(pdev, NIG_REG_STATUS_INTERRUPT_PORT0); 839 nig_status_port = REG_RD(pdev, NIG_REG_STATUS_INTERRUPT_PORT1); 900 mask_val=REG_RD(pdev, port_reg_name); 932 nig_mask = REG_RD(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev)); 994 val = REG_RD(pdev, IGU_REG_ATTENTION_ACK_BITS); 1011 val = REG_RD(pdev,CFC_REG_CFC_INT_STS); 1023 valc = REG_RD(pdev,CFC_REG_CFC_INT_STS_CLR); 1028 u32_t val = REG_RD(pdev,PXP_REG_PXP_INT_STS_0); 1063 val = REG_RD(pde [all...] |
H A D | bnxe_hw_debug.c | 70 val = REG_RD(pdev, MISC_REG_CHIP_NUM); 77 val = REG_RD(pdev,TM_REG_EN_LINEAR0_TIMER); 87 val = REG_RD(pdev,TM_REG_LIN0_SCAN_ON); 97 val = REG_RD(pdev,TM_REG_EN_LINEAR1_TIMER); 107 val = REG_RD(pdev,TM_REG_LIN1_SCAN_ON); 128 val = REG_RD(pdev, MISC_REG_CHIP_NUM); 147 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVLF); 151 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVL_MAX); 155 val = REG_RD(pdev,DORQ_REG_DB_DIS_CNTR0); 192 chip_num = REG_RD(pde [all...] |
H A D | lm_mcp.c | 145 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); 171 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); 191 val = REG_RD(pdev, shmem + validity_offset); 241 val = REG_RD(pdev, MISC_REG_DRIVER_CONTROL_15); 285 val_rd = REG_RD(pdev, GRCBASE_MCP + 0x9c); 320 val= REG_RD(pdev, GRCBASE_MCP + 0x9c); 1106 reg = REG_RD(pdev, offset); 1110 if( REG_RD(pdev, offset) != reg )
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H A D | lm_sb.c | 104 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WOMASK(pdev)); 120 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WMASK(pdev)); 679 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0) + group_idx*16); 681 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0) + group_idx*16); 683 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0) + group_idx*16); 685 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0) + group_idx*16); 689 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0) + group_idx*4); 984 while (!(REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) 989 if (!(REG_RD(pdev, igu_addr_ack) & sb_bit)) 1005 while ((REG_RD(pde [all...] |
H A D | lm_power.c | 376 val = REG_RD(pdev, emac.emac_mode); 381 val = REG_RD(pdev, rpm.rpm_config); 449 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); 463 u32_t own_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); 474 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset);
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H A D | lm_devinfo.c | 176 val = REG_RD(pdev, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 219 val = REG_RD(pdev, BAR_ME_REGISTER); 590 pdev->hw_info.grc_didvid = REG_RD(pdev, (PCICFG_OFFSET + PCICFG_VENDOR_ID_OFFSET)); 612 tr_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ); 613 tw_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE); 614 m_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 632 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_NUM); 636 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_TYPE); 654 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_REV); 675 val=REG_RD(PFDE [all...] |
H A D | lm_phy.c | 77 return REG_RD(cb, reg_addr); 255 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); 274 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); 295 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); 329 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); 347 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); 372 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE);
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H A D | lm_dcbx.c | 2799 *buff = REG_RD(pdev, 3134 *buff = REG_RD(pdev, 3182 *buff = REG_RD(pdev, 3401 *buff = REG_RD(pdev, 3627 *buff = REG_RD(pdev, 4151 *buff = REG_RD(pdev, 4474 *buff = REG_RD(pdev,
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H A D | lm_stats.c | 591 val = REG_RD(pdev, HC_REG_INT_MASK + 4*PORT_ID(pdev) ); 710 dummy = REG_RD( pdev, emac_base + reg_start[i]+(j*sizeof(u32_t))) ; /*Clear stats registers by reading from from ReadClear RX/RXerr/TX STAT banks*/ 3712 pdev->vars.stats.stats_collect.stats_hw.misc_stats_query.tx_lpi_count = REG_RD(pdev, eee);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/ |
H A D | bnxe_fw_funcs.c | 43 u32_t curr_cos = REG_RD(pdev, QM_REG_QVOQIDX_0 + q_num * 4); 70 reg_bit_map = REG_RD(pdev, reg_addr); 75 reg_bit_map = REG_RD(pdev, reg_addr); 82 reg_bit_map = REG_RD(pdev, reg_addr);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/ |
H A D | bnxe_clc.c | 67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg) macro 69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg) 162 REG_RD(cb, shmem2_base + \ 347 u32 val = REG_RD(cb, reg); 356 u32 val = REG_RD(cb, reg); 380 REG_RD(cb, params->lfa_base + 395 link_status = REG_RD(cb, params->shmem_base + 424 saved_val = REG_RD(cb, params->lfa_base + 433 saved_val = REG_RD(cb, params->lfa_base + 442 saved_val = REG_RD(c [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ |
H A D | ecore_init.h | 203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr); 268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i]. 280 reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP);
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H A D | ecore_init_ops.h | 272 REG_RD(pdev, addr); 540 val = REG_RD(pdev, write_arb_addr[i].l); 544 val = REG_RD(pdev, write_arb_addr[i].add); 548 val = REG_RD(pdev, write_arb_addr[i].ubound); 609 val = REG_RD(pdev, PCIE_REG_PCIER_TL_HDR_FC_ST);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/ |
H A D | lm_vf.c | 2947 val=REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); 2991 val = REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); 3341 tq_freed_cnt_last = tq_freed_cnt_start = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); 3342 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); 3348 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); 3349 tq_freed_cnt_last = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); 3392 inernal_freed_crd_last = inernal_freed_crd_start = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_freed); 3393 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); 3394 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); 3402 credit_last = REG_RD(PFDE [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/ |
H A D | lm5710.h | 518 *(_unicore_intr_val_ptr) = REG_RD(_pdev, _nig_reg_name); \ 4088 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro 4101 #define REG_RD(_pdev, _reg_offset) \ macro 4140 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro 4181 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro 4230 (REG_RD(_pdev, LM_SHMEM2_ADDR(_pdev, size)) > OFFSETOF(struct shmem2_region, field))) 4305 db_fill=REG_RD(pf_dev,DORQ_REG_DQ_FILL_LVLF); 4319 db_fill=REG_RD(pf_dev,DORQ_REG_DQ_FILL_LVLF);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/ |
H A D | lm_vf.c | 530 val=REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); 574 val = REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION);
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