/******************************************************************************
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright 2014 QLogic Corporation
* The contents of this file are subject to the terms of the
* QLogic End User License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*
*
* Module Description:
*
*
* History:
* 03/21/03 Hav Khauv Inception.
******************************************************************************/
#include "lm5710.h"
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static lm_status_t
{
u8_t port_num = PORT_ID(pdev); /* TBD - E1H: nvram lock � DOES NOT scale to 8 functions! (only 4 clients)
* 1. Can we assume no concurrent access by control applications?
* 2. If not, the MISC lock is our backup */
val = 0;
/* Request access to the flash interface. */
for(j = 0; j < cnt*10; j++)
{
{
break;
}
}
{
}
else
{
DbgBreakMsg("Cannot get access to nvram interface.\n");
}
return lm_status;
} /* acquire_nvram_lock */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static void
{
/* Relinquish nvram interface. */
val = 0;
for(j = 0; j < cnt; j++)
{
{
break;
}
}
} /* release_nvram_lock */
#if 0
/*******************************************************************************
* Description:
*
* Return:
*
******************************************************************************/
static lm_status_t
{
/* Need to clear DONE bit separately. */
/* Issue a write enable command. */
for(j = 0; j < cnt; j++)
{
if(val & MCPR_NVM_COMMAND_DONE)
{
break;
}
}
return lm_status;
} /* enable_nvram_write */
/*******************************************************************************
* Description:
*
* Return:
*
******************************************************************************/
static lm_status_t
{
/* Need to clear DONE bit separately. */
/* Issue a write disable command. */
for(j = 0; j < cnt; j++)
{
if(val & MCPR_NVM_COMMAND_DONE)
{
break;
}
}
return lm_status;
} /* disable_nvram_write */
#endif /* 0 */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static lm_status_t
{
/* Enable both bits, even on read. */
REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN);
return LM_STATUS_SUCCESS;
} /* enable_nvram_access */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static lm_status_t
{
/* Disable both bits, even after read. */
REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val & ~(MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
return LM_STATUS_SUCCESS;
} /* disable_nvram_access */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static lm_status_t
{
/* Build the command word. */
/* Need to clear DONE bit separately. */
/* Address of the NVRAM to read from. */
/* Issue a read command. */
/* Wait for completion. */
for(j = 0; j < cnt; j++)
{
if(val & MCPR_NVM_COMMAND_DONE)
{
/* Change to little endian. */
#if defined(LITTLE_ENDIAN)
#endif
break;
}
}
return lm_status;
} /* nvram_read_dword */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
static lm_status_t
{
/* Build the command word. */
/* Change to little endian. */
#if defined(LITTLE_ENDIAN)
#endif
/* Need to clear DONE bit separately. */
/* Write the data. */
/* Address of the NVRAM to write to. */
/* Issue the write command. */
/* Wait for completion. */
for(j = 0; j < cnt; j++)
{
if(val & MCPR_NVM_COMMAND_DONE)
{
break;
}
}
return lm_status;
} /* nvram_write_dword */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
{
{
DbgBreakMsg("Invalid paramter.\n");
return LM_STATUS_FAILURE;
}
// TODO what is the nvram total size
{
DbgBreakMsg("Invalid paramter.\n");
return LM_STATUS_FAILURE;
}
/* Request access to the flash interface. */
if(lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
/* Enable access to flash interface */
if(lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
/* Read the first word. */
{
/* Advance to the next dword. */
ret_buf++;
cmd_flags = 0;
}
if(lm_status == LM_STATUS_SUCCESS)
{
}
/* Disable access to flash interface */
return lm_status;
} /* lm_nvram_read */
/*******************************************************************************
* Description:
*
* Return:
******************************************************************************/
{
if(offset & 0x03)
{
DbgBreakMsg("Invalid paramter.\n");
return LM_STATUS_FAILURE;
}
// TODO what is the nvram total size
{
DbgMessage(pdev, FATAL, "lm_nvram_write failed ! buf_size %d larger than NVM total_size %d\n", buf_size, pdev->hw_info.flash_spec.total_size);
DbgBreakMsg("Failed to write to NVM! Attemp to write to offset larger than NVM total size !\n");
return LM_STATUS_FAILURE;
}
/* Request access to the flash interface. */
if(lm_status != LM_STATUS_SUCCESS)
return lm_status;
/* Enable access to flash interface */
if(lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
written_so_far = 0;
while (written_so_far < buf_size)
{
ptr32++;
addr += 4;
written_so_far += 4;
cmd_flags = 0;
}
/* Disable access to flash interface */
return lm_status;
} /* lm_nvram_write */