/*******************************************************************************
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright 2014 QLogic Corporation
* The contents of this file are subject to the terms of the
* QLogic End User License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*
*
* Module Description:
* This file contains functions that handle HW and FW attention
*
******************************************************************************/
#include "lm5710.h"
#include "general_atten_bits.h"
#include "aeu_inputs.h"
#include "command.h"
{
{
}
}
/**
* @description
* called from attention handling routines, checks if the
* attention received is an error which is recoverable via
* process kill. If error recovery is disabled this
* function always returns FALSE;
*
* @param pdev
* @param attn_sig : values of the after_invert registers read
* in the misc that indicate which attention
* occured
*
*
* @return u8_t TRUE: attention requires process_kill. FALSE o/w
*/
{
u32_t i;
{
return FALSE;
}
{
/* Parity Error... Assuming we only enable parities we can deal with
* this is a recoverable error...
*/
for (i = 0; i < arr_size; i++)
{
}
/* TODO: maybe get GRCDump here in the future... */
return TRUE;
}
/* HW Attentions (other than parity ) */
{
/* QM Interrupt is recoverable */
{
for (i = 0; i < arr_size; i++)
{
}
return TRUE;
}
}
{
{
for (i = 0; i < arr_size; i++)
{
}
return TRUE;
}
}
return FALSE;
}
{
if (!CHIP_IS_E1x(pdev))
{
| PXP_PXP_INT_MASK_1_REG_HST_VF_DISABLED_ACCESS /*Temporary solution*/
| PXP_PXP_INT_MASK_1_REG_HST_PERMISSION_VIOLATION) /*Win8 MMIO (security test)???*/);
}
/* CFC_REG_CFC_INT_MASK see in init_cfc_common */
//mask read length error interrupts in brb for parser (parsing unit and 'checksum and crc' unit)
//these errors are legal (PU reads fixe length and CAC can cause read length error on truncated packets)
//REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_0 ,0);
//REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_1 ,0);
//REG_WR(pdev,USEM_REG_USEM_INT_MASK_0 ,0);
//REG_WR(pdev,USEM_REG_USEM_INT_MASK_1 ,0);
//REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_0 ,0);
//REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_1 ,0);
if (!CHIP_IS_E1x(pdev))
{
}
//REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_0 ,0);
//REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_1 ,0);
//REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_MISC_INT_MASK ,0);
//MASK BIT 3,4
}
{
typedef struct _block_mask_info_t
{
{
{ ATC_REG_ATC_INT_MASK, { 0,
0,
6 } },
{ BRB1_REG_BRB1_INT_MASK, { 19,
19,
19} },
{ CCM_REG_CCM_INT_MASK, { 11,
11,
11 } },
{ CDU_REG_CDU_INT_MASK, { 7,
7,
7 } },
{ CFC_REG_CFC_INT_MASK, { 2,
2,
2 } },
{ CSDM_REG_CSDM_INT_MASK_0, { 32,
32,
32 } },
{ CSDM_REG_CSDM_INT_MASK_1, { 10,
10,
11 } },
#if 0
{ CSEM_REG_CSEM_INT_MASK_0, { 32,
32,
32 } },
{ CSEM_REG_CSEM_INT_MASK_1, { 10,
11,
11} },
{ DBG_REG_DBG_INT_MASK, { 2,
2,
2 } },
#endif //0
{ DMAE_REG_DMAE_INT_MASK, { 2,
2,
2 } },
{ DORQ_REG_DORQ_INT_MASK, { 5,
5,
6 } },
#if 0
{ HC_REG_HC_INT_MASK, { 7,
7,
7 } },
#endif //0
{ IGU_REG_IGU_INT_MASK, { 0,
0,
11 } },
#if 0
{ MISC_REGISTERS_MISC_INT_MASK, { 4,
4,
8 } },
{ NIG_REGISTERS_NIG_INT_MASK_0, { 32,
32,
32 } },
{ NIG_REGISTERS_NIG_INT_MASK_1, { 2,
4,
14 } },
{ PB_REGISTERS_PB_INT_MASK, { 2,
2,
2} },
#endif // 0
{ PBF_REG_PBF_INT_MASK, { 5,
5,
7 } },
{ PGLUE_B_REG_PGLUE_B_INT_MASK, { 0,
0,
9 } },
#if 0
{ PRS_REG_PRS_INT_MASK, { 1,
1,
1 } },
#endif // 0
{ PXP2_REG_PXP2_INT_MASK_0, { 25,
32,
32 } },
#if 0
{ PXP2_REG_PXP2_INT_MASK_1, { 0,
6,
16} },
#endif //0
{ PXP_REG_PXP_INT_MASK_0, { 32,
32,
32 } },
{ PXP_REG_PXP_INT_MASK_1, { 5,
5,
8 } },
{ QM_REG_QM_INT_MASK, { 2,
2,
14 } },
#if 0
1,
1} },
{ SRC_REG_SRC_INT_MASK, { 1,
3,
3 } },
#endif //0
{ TCM_REG_TCM_INT_MASK, { 11,
11,
11 } },
{ TM_REG_TM_INT_MASK, { 1,
1,
1} },
{ TSDM_REG_TSDM_INT_MASK_0, { 32,
32,
32 } },
{ TSDM_REG_TSDM_INT_MASK_1, { 10,
10,
11 } },
#if 0
{ TSEM_REG_TSEM_INT_MASK_0, { 32,
32,
32 } },
{ TSEM_REG_TSEM_INT_MASK_1, { 10,
11,
13 } },
#endif // 0
{ UCM_REG_UCM_INT_MASK, { 11,
11,
11} },
{ USDM_REG_USDM_INT_MASK_0, { 32,
32,
32 } },
{ USDM_REG_USDM_INT_MASK_1, { 10,
10,
11 } },
#if 0
{ USEM_REG_USEM_INT_MASK_0, { 32,
32,
32 } },
{ USEM_REG_USEM_INT_MASK_1, { 10,
11,
11 } },
#endif //0
{ VFC_REG_VFC_INT_MASK, { 0,
0,
1 } },
{ XCM_REG_XCM_INT_MASK, { 14,
14,
14 } },
{ XSDM_REG_XSDM_INT_MASK_0, { 32,
32,
32 } },
{ XSDM_REG_XSDM_INT_MASK_1, { 10,
10,
11} },
#if 0
{ XSEM_REG_XSEM_INT_MASK_0, { 32,
32,
32 } },
{ XSEM_REG_XSEM_INT_MASK_1, { 10,
11,
13 } } ,
#endif // 0
}; // init_mask_values_arr
{
return;
}
if CHIP_IS_E1( pdev )
{
chip_idx = 0; // E1.0
}
else if CHIP_IS_E1H(pdev)
{
}
else if CHIP_IS_E2E3(pdev)
{
}
else
{
// New chip!!!
}
{
if( mask_value )
{
}
}
/*
REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0xffffffff);
if (IS_E2(pdev)) {
REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0xff);
} else {
REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0x1f);
}
REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0x1f);
REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0x3);
REG_WR(pdev,QM_REG_QM_INT_MASK ,0x3);
REG_WR(pdev,TM_REG_TM_INT_MASK ,0x1);
REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0xffffffff);
REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0x3ff);
REG_WR(pdev,XCM_REG_XCM_INT_MASK,0x3fff);
//REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_0 ,0);
//REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_1 ,0);
REG_WR(pdev,USDM_REG_USDM_INT_MASK_0 ,0xffffffff);
REG_WR(pdev,USDM_REG_USDM_INT_MASK_1 ,0x3ff);
REG_WR(pdev,UCM_REG_UCM_INT_MASK ,0x7ff);
//REG_WR(pdev,USEM_REG_USEM_INT_MASK_0 ,0);
//REG_WR(pdev,USEM_REG_USEM_INT_MASK_1 ,0);
REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0x3);
REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_0 ,0xffffffff);
REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_1 ,0x3ff);
REG_WR(pdev,CCM_REG_CCM_INT_MASK ,0x7ff);
//REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_0 ,0);
//REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_1 ,0);
REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_0,0xffffffff);
REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_0 ,0xffffffff);
REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_1 ,0x3ff);
REG_WR(pdev,TCM_REG_TCM_INT_MASK ,0x7ff);
//REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_0 ,0);
//REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_1 ,0);
REG_WR(pdev,CDU_REG_CDU_INT_MASK ,0x7f);
REG_WR(pdev,DMAE_REG_DMAE_INT_MASK ,0x3);
//REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_MISC_INT_MASK ,0);
//MASK BIT 3,4
REG_WR(pdev,PBF_REG_PBF_INT_MASK ,0x1f);
*/
// disable MCP's attentions
}
{
// mask the pxp attentions
if (CHIP_IS_E1x(pdev))
{
}
else
{
}
/* We never unmask this register so no need to re-mask it*/
//REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_1,0x3f); // 32 bits
}
{
//pass over all latched attentions
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x1;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x2;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x4;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x8;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x10;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x20;
// we check if nig reset was done
if( b_nig_reset_called )
{
}
if (!CHIP_IS_E1(pdev))
{
// in non E1 we can verify it is mcp cause (due to nig probably)
{
}
}
DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_TIMEOUT_GRC received!!! val=0x%08x master=0x%x func=0x%x addr=0x%xx4=0x%X)\n"
// NOTE: we ignore b_nig_reset_called and ASSERT only according to grc_timeout_max_ignore value (default is 0x10)
// if we are here it means we ignore the ASSERT inc counter
if( grc_timeout_cnt >= grc_timeout_max_ignore )
{
}
else
{
}
if( b_assert )
{
DbgBreakIf(1);
}
if( b_nig_reset_called )
{
// we reset the flag (we "allow" one timeout after nig reset)
}
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x40;
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x80;
DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_ROM_PARITY_MCP received!!!\n");
/* For E2, at the time this code was written (e2-bringup ) the parity is (somehow) expected */
if (CHIP_IS_E1x(pdev))
{
DbgBreakIfAll(1);
}
else
{
DbgBreakIf(1);
}
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x100;
DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_UM_RX_PARITY_MCP received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x200;
DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_UM_TX_PARITY_MCP received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
latch_bit_to_clr = 0x400;
DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_SCPAD_PARITY_MCP received!!!\n");
DbgBreakIfAll(1);
}
}
{
/* processing of highest 8-15 bits of 8 "hard-wired" attention signals toward IGU.
Excluding NIG & PXP "close the gates"
! No need to lock here since this is an uncommon group whether there is a recovery procedure or not.
Signal name Bit position SOURCE Type Required Destination
-----------------------------------------------------------------------------
SW timer#4 port0 D9 MISC Event MCP -> Ignore!
GPIO#2 port0 D10 MISC Event MCP
GPIO#3 port0 D11 MISC Event MCP
GPIO#4 port0 D12 MISC Event MCP
*/
//TODO: for the required attn signals, need to "clean the hw block" (INT_STS_CLR..)
{
#if 0 // Timer 4 is being used by OCBB now
{
//DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_SW_TIMER_4_FUNC!\n");
//to deal with this signal, add dispatch func call here
}
#endif
if (assertion_proc_flgs & GPIO_2_FUNC)
{
//to deal with this signal, add dispatch func call here
}
if (assertion_proc_flgs & GPIO_3_FUNC)
{
//to deal with this signal, add dispatch func call here
}
if (assertion_proc_flgs & GPIO_4_FUNC)
{
// Will be handled in deassertion
}
{
}
{
}
{
}
}
else
{
{
//DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_SW_TIMER_4_FUNC1!\n");
//to deal with this signal, add dispatch func call here
}
if (assertion_proc_flgs & GPIO_2_FUNC1)
{
//to deal with this signal, add dispatch func call here
}
if (assertion_proc_flgs & GPIO_3_FUNC1)
{
//to deal with this signal, add dispatch func call here
}
if (assertion_proc_flgs & GPIO_4_FUNC1)
{
// Will be handled in deassertion
}
{
}
{
}
{
}
}
}
{
// save nig interrupt mask and set it back later
{
//read the status interrupt of the NIG for the appropriate port (will do read-modify-write)
//pass over each of the 24 NIG REG to find out why the NIG attention was asserted.
//every unicore interrupt read, in case it differs from the corresponding bit in the
//NIG_REG_STATUS_INTERRUPT_PORT0, then we need to assign the value read into the apporpriate bit
// in NIG_REG_STATUS_INTERRUPT_PORT0 register.
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_MI_INT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_MI_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_CFG_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_LINK_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_ATTN, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_REMOTEMDIOREQ, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_LINK10G, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS_SIZE);
//write back the updated status interrupt of the NIG for the appropriate port.
}
else
{
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_MI_INT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_MI_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_CFG_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_LINK_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_ATTN, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_REMOTEMDIOREQ, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_LINK10G, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT_SIZE);
//HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET_SIZE);
HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS_SIZE);
}
}
{
DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: assertion_proc_flgs:%d\n", assertion_proc_flgs);
//mask only appropriate attention output signals from configured routing and unifier logic toward IGU.
//in both leading & trailing latch.
//mask non-hard-wired dynamic groups only
//mask relevant AEU attn lines
// mask assert_flgs new mask
//legal: 0 0 -> 0
// 1 0 -> 1
// 1 1 -> 0
//ASSERT: 0 1 -> this won't change us thanks to & ~
// read the hw current mask value
//changed rrom XOR to & ~
DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: BEFORE: aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
//changed rrom XOR to & ~
DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: AFTER : aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
//update the bits states
// state assert_flgs new state
//legal: 0 0 -> 0
// 0 1 -> 1
// 1 0 -> 1
//error: 1 1 -> this won't change us thanks to |
DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: BEFORE: attn_state:0x%x\n", pdev->vars.attn_state);
//changed from XOR to OR for safety
DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: AFTER : attn_state:0x%x\n", pdev->vars.attn_state);
//process only hard-wired lines in case any got up
{
}
// now handle nig
{
// save nig interrupt mask and set it back later
// we'll handle the attention only if mask is not 0
// if mask is 0, it means that "old" and irrelevant is sent
// and we should not hnalde it (e.g. CQ48990 - got link down event after loopback mode was set).
if( nig_mask )
{
}
else
{
}
}
//parallel write to IGU to set the attn_ack for _all asserted_ lines.
// attntion bits set
{
}
else
{
{
}
else
{
/* GRC ACCESS: */
/* Write the Data, then the control */
/* [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:14] = 0; [13:12] = PF number) */
((cmd_addr << IGU_CTRL_REG_ADDRESS_SHIFT) |
}
}
// now set back the mask
{
{
// Verify that IGU ack through BAR was written before restoring NIG mask.
// This loop should exit after 2-3 iterations max.
do
{
}
if (!val)
{
}
}
}
}
{
// TODO add defines here
if (val) {
// CFC error attention
if (val & 0x2)
{
//DbgBreakIfAll(1);
}
}
return val;
}
{
// TODO add defines here
// RQ_USDMDP_FIFO_OVERFLOW attention
if (val & 0x18000)
{
DbgBreakIfAll(1);
}
}
/*
*Function Name:lm_spio5_attn_everest_processing
*
*Parameters:
*
*Description:
* Indicates fan failure on specific external_phy_config (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
*Returns:
*
*/
{
// Special fan failure handling for boards with external PHY SFX7101 (which include fan)
// mask flags so we won't get this attention anymore
// change phy_type to type failure (under phy lock)
// Set external phy type to failure for MCP to know about the failure
DbgMessage(pdev, WARN, "lm_spio5_attn_everest_processing: external_phy_type 0x%x\n",ext_phy_config);
// Indicate "link-down". elink_hw_reset_phy takes care of the physical part, but part of the function
// masks attentions, which means we won't get a link event from anywhere else. Therefore we need to
// indicate link down at this point to OS... to supress traffic and upload toe connections...
// we do this under lock since we change the link status...
// write to the event log!
}
// Check current fan failure state - report in case signaled.
{
{
return;
}
{
}
}
// Change PMF or link change
// PMF sent link updates to all func (but himself) OR I become a PMF from MCP notification
// on some cases PMF sends link event to himself as well if errors occured in the mac.
{
DbgMessage(pdev, WARN, "lm_pmf_or_link_event: sync general attention received!!! for func%d\n",FUNC_ID(pdev));
// sync with link
{
//pmf migration
// load stat from MCP
// Connect to NIG attentions
{
}
else
{
if (CHIP_IS_E3(pdev))
{
}
}
{
}
}
}
{
if( !IS_MULTI_VNIC(pdev) )
{
DbgBreakIf(1);
return;
}
// read shemem
// Read new mf config from shemem
{
{
// TODO - receive packets fronm another machine when link is down - expected - miniport drop packets
// TBD - disable RX & TX
}
else
{
// TBD - enable RX & TX
}
}
{
{
DbgBreakIf(1);
return;
}
}
/* Report results to MCP */
if (dcc_event)
{
// unknown event
lm_status = lm_mcp_cmd_send_recieve( pdev, lm_mcp_mb_header, DRV_MSG_CODE_DCC_FAILURE, 0, MCP_CMD_DEFAULT_TIMEOUT, &fw_resp ) ;
}
else
{
// we are done
if( LM_STATUS_SUCCESS == lm_status )
{
}
lm_status = lm_mcp_cmd_send_recieve( pdev, lm_mcp_mb_header, DRV_MSG_CODE_DCC_OK, 0, MCP_CMD_DEFAULT_TIMEOUT, &fw_resp ) ;
//bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
}
}
{
//update CMNG data from SHMEM
//acknoledge the MCP event
lm_mcp_cmd_send_recieve(pdev,lm_mcp_mb_header, DRV_MSG_CODE_SET_MF_BW_ACK, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
if ( mcp_resp != FW_MSG_CODE_SET_MF_BW_DONE)
{
goto _exit;
}
//indicate link change to OS, since sync_link_status does not generate a link event for the PMF.
//notify all functions
return lm_status;
}
{
{
// We should never get here...
return LM_STATUS_FAILURE;
}
do
{
if( DRV_INFO_CUR_VER != ver )
{
// We don't support this interface verison
break;
}
drv_info_op = ( GET_FLAGS( val, DRV_INFO_CONTROL_OP_CODE_MASK ) ) >> DRV_INFO_CONTROL_OP_CODE_SHIFT;
if( LM_STATUS_SUCCESS != lm_status )
{
break;
}
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_info_host_addr_lo), pdev->vars.stats.stats_collect.drv_info_to_mfw.drv_info_to_mfw_phys_addr.as_u32.low );
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_info_host_addr_hi), pdev->vars.stats.stats_collect.drv_info_to_mfw.drv_info_to_mfw_phys_addr.as_u32.high );
} while(0);
lm_status = lm_mcp_cmd_send_recieve( pdev, lm_mcp_mb_header, drv_msg, 0, MCP_CMD_DEFAULT_TIMEOUT, &fw_resp );
return lm_status;
}
{
/*TODO: Have to do some processing based on fi the pF is enabled or disabled*/
///indicate "link-down"
/* Report results to MCP */
///ACK the MCP message
if(status == LM_STATUS_SUCCESS)
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_OK, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
else
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_FAILURE, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
return status;
}
{
//Reconfigure rate-limit
/* Other than vlan tag what are other UFP specific data?
* Should we read the priority etc
*/
/* get ovlan if we're in switch-dependent mode... */
/* modify the NIG LLH registers */
/* send function update ramrod to change the tag in the FW */
/* Report results to MCP */
///ACK the MCP message
if(status == LM_STATUS_SUCCESS)
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_OK, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
else
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_FAILURE, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
}
{
///read FUNC-DISABLED and FUNC-DELETED from func_mf_cfg
{
{
if (lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
}
else
{
#ifdef EDIAG
#else
#endif
if (lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
}
}
else if (event & DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)
{
//lm_hardware_mf_info_t *mf_info = &pdev->hw_info.mf_info;
//mf_info->min_bw[vnic] = (GET_FLAGS(config, FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
//mf_info->max_bw[vnic] = (GET_FLAGS(config, FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
/* this function reads the bw configuration and does the necessary processing..
* only drawback is it reads the configuration for all the functions?
*. todo check if we should be using this or not...
*/
if (lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
}
return lm_status;
}
{
/* get ovlan if we're in switch-dependent mode... */
/* modify the NIG LLH registers */
/* send function update ramrod to change the tag in the FW */
/* Report results to MCP */
if(lm_status == LM_STATUS_SUCCESS)
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
else
lm_mcp_cmd_send_recieve(pdev, lm_mcp_mb_header, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0, MCP_CMD_DEFAULT_TIMEOUT, &mcp_resp);
}
#ifndef EDIAG
{
/* Todo get the priority from somewhere */
/* send function update ramrod to change the tag in the FW */
//data->sd_vlan_force_pri_val = mm_cpu_to_le16((u16_t)new_priority);
/*Todo Report results to mcp?*/
}
#endif
{
#ifdef EDIAG
#else
#endif
if (lm_status != LM_STATUS_SUCCESS)
{
return lm_status;
}
return lm_status;
}
{
// reset attention
// drv_status
&val);
// E1H NIG status sync attention mapped to group 4-7
{
// Read VFs
for (i = 0; i < ARRSIZE(mcp_vf_disabled); i++)
{
}
DbgMessage(pdev, FATAL, "lm_generic_event: DRV_STATUS_VF_DISABLED received for vfs bitmap %x %x!!!\n", mcp_vf_disabled[0], mcp_vf_disabled[1]);
// SHMULIK, PLACE YOUR CODE HERE ( Handle only VFs of this PF )
// Acknoledge the VFs you handled ( This array is per PF driver on path )
for (i = 0; i < ARRSIZE(mcp_vf_disabled) ; i++)
{
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t,drv_ack_vf_disabled[FUNC_MAILBOX_ID(pdev)][i]), mcp_vf_disabled[i]);
}
0,
&fw_resp);
return; // YANIV - DEBUG @@@!!!
}
if(IS_MULTI_VNIC(pdev))
{
{
}
{
}
//if val has any NIV event flags, call lm_niv_event
{
}
}
{
}
// NOTE:
// once we have events such as DCC and NIV, this condition doesn't stand anymore
// we might get here TRUE although we are in MULTI_VNIC AND we are not PMF
// and this is not for link change or pmf migration
// the potential problem (redundant link report to OS CQ60223)
// is resolved in "lm_link_report" function that check current link
// with previous reported link
/* Check if pmf or link event function should be called: */
/* PMF or link event */
{
DbgMessage(pdev, WARN, "lm_generic_event: ELINK_PERIODIC_FLAGS_LINK_EVENT func_id=%d!!!\n", func_id );
/* sync with link */
}
if(call_pmf_or_link)
{
}
{
}
{
}
}
{
//pass over all attention generals which are wired to a dynamic group of the lower 8 bits
if ( offset & sig_word_aft_inv)
{
DbgMessage(pdev, FATAL, "lm_gen_attn_everest_processing: TSTORM_FATAL_ASSERT_ATTENTION_BIT received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
DbgMessage(pdev, FATAL, "lm_gen_attn_everest_processing: USTORM_FATAL_ASSERT_ATTENTION_BIT received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
DbgMessage(pdev, FATAL, "lm_gen_attn_everest_processing: CSTORM_FATAL_ASSERT_ATTENTION_BIT received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
DbgMessage(pdev, FATAL, "lm_gen_attn_everest_processing: XSTORM_FATAL_ASSERT_ATTENTION_BIT received!!!\n");
DbgBreakIfAll(1);
}
if ( offset & sig_word_aft_inv)
{
DbgMessage(pdev, FATAL, "lm_gen_attn_everest_processing: MCP_FATAL_ASSERT_ATTENTION_BIT received mcp_check=0x%x!!!\n" , val);
DbgBreakIfAll(1);
}
// E1H NIG status sync attention mapped to group 4-7
if (!CHIP_IS_E1(pdev))
{
// PMF change or link update
if ( offset & sig_word_aft_inv)
{
}
}
}
{
u8_t i;
//Read the 128 attn signals bits after inverter
{
}
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: attn_sig_aft_invert_1:0x%x; attn_sig_aft_invert_2:0x%x; attn_sig_aft_invert_3:0x%x; attn_sig_aft_invert_4:0x%x,attn_sig_aft_invert_5:0x%x\n",
attn_sig_af_inv_arr[4]);
}
{
//guard against dynamic change of attn lines - 15 interations max
//the main idea here is to assure that we work on synchronized snapshots of the attn_bits and
//attn_ack and avoid a faulty scenario where attn_ack we read in sanpshot #2 corresponds to attn_bits
//of snapshot #1 which occured on different time frames.
do
{
//the lcl_attn_sb_index differs from the real local attn_index in the pdev since in this while loop it could
//have been changed, we don't save it locally, and thus we will definitely receive an interrupt in case the
//while condition is met.
"lm_get_attn_info: def_sb->attn_bits:0x%x, def_sb->attn_ack:0x%x, attn_bits:0x%x, attn_ack:0x%x\n",
*attn_ack);
}
{
// TODO add defines here
if (val) {
{
// DORQ discard attention
}
{
// DORQ discard attention
}
}
return val;
}
{
u8_t i = 0;
DbgBreakIf(!pdev);
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: deassertion_proc_flgs:%d\n", deassertion_proc_flgs);
//acquire split lock for attention signals handling
{
if (lm_status == LM_STATUS_SUCCESS)
{
/* Continue only on success... */
/* Disable HW interrupts */
/* In case of recoverable error don't handle attention so that
* other functions get this parity as well.
*/
return;
}
/* Recovery failed... we'll keep going, and eventually hit
* the attnetion and assert...
*/
}
//For all deasserted groups, pass over entire attn_bits after inverter and if they
// are members of that particular gruop, treat each one of them accordingly.
{
{
for (i = 0; i < ARRSIZE(group_mask_arr); i++)
{
}
DbgMessage(pdev, WARN, "lm_handle_deassertion_processing: group #%d got attention on it!\n", index);
DbgMessage(pdev, WARN, "lm_handle_deassertion_processing: mask1:0x%x, mask2:0x%x, mask3:0x%x, mask4:0x%x,mask5:0x%x\n",
group_mask_arr[0],
group_mask_arr[1],
group_mask_arr[2],
group_mask_arr[3],
group_mask_arr[4]);
DbgMessage(pdev, WARN, "lm_handle_deassertion_processing: attn1:0x%x, attn2:0x%x, attn3:0x%x, attn4:0x%x,attn5:0x%x\n",
attn_sig_af_inv_arr[4]);
{
}
// DQ attn
{
}
// CFC attn
{
}
// PXP attn
{
}
// SPIO 5 bit in register 0
{
}
// GPIO3 bits in register 0
{
// Handle it only for PMF
{
}
}
//TODO: attribute each attention signal arrived and which is a member of a group and give it its own
// specific treatment. later, for each attn, do "clean the hw block" via the INT_STS_CLR.
//Check for lattched attn signals
{
}
// general hw block attention
i = 0;
i = 1;
i = 2;
i = 4;
}
if ( (mask_arr_val[0]) ||
(mask_arr_val[2] & ~(AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT | AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT)) ||
(mask_arr_val[4]) )
{
DbgBreakIfAll(1);
}
// general hw block mem prty
i = 0;
i = 1;
i = 2;
i = 4;
if ( (mask_arr_val[0]) ||
(mask_arr_val[1]) ||
(mask_arr_val[2]) ||
(mask_arr_val[4]) )
{
DbgBreakIfAll(1);
}
}
}
//release split lock
//TODO: the attn_ack bits to clear must be passed with '0'
//val = deassertion_proc_flgs;
// attntion bits clear
{
}
else
{
{
}
else
{
/* GRC ACCESS: */
/* Write the Data, then the control */
/* [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:14] = 0; [13:12] = PF number) */
((cmd_addr << IGU_CTRL_REG_ADDRESS_SHIFT) |
}
}
//unmask only appropriate attention output signals from configured routing and unifier logic toward IGU.
//in both leading & trailing latch.
//unmask non-hard-wired dynamic groups only
//unmask relevant AEU attn lines
// mask deassert_flgs new mask
//legal: 0 0 -> 0
// 0 1 -> 1
// 1 0 -> 1
//ASSERT: 1 1 -> this won't change us thanks to the |
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: BEFORE: aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
//changed from XOR to OR for safely
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: AFTER : aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
//update the attn bits states
// state deassert_flgs new state
//legal: 0 0 -> 0
// 1 0 -> 1
// 1 1 -> 0
//ASSERT: 0 1 -> this won't change our state thanks to & ~ !
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: BEFORE: attn_state:0x%x\n", pdev->vars.attn_state);
//changed from XOR to : AND ~ for safety
DbgMessage(pdev, INFORM, "lm_handle_deassertion_processing: AFTER : attn_state:0x%x\n", pdev->vars.attn_state);
}