d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#include "57712_reg.h"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* LED Blink rate that will achieve ~15.9Hz */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MSLEEP(cb, ms) elink_cb_udelay(cb, 1000*ms)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define USLEEP(cb, us) elink_cb_udelay(cb, us)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define REG_RD(cb, reg) elink_cb_reg_read(cb, reg)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define REG_WR_DMAE(cb, offset, wb_data, len) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_reg_wb_write(cb, offset, wb_data, len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define REG_RD_DMAE(cb, offset, wb_data, len) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_reg_wb_read(cb, offset, wb_data, len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SET_MULT_GPIO elink_cb_gpio_mult_write
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SET_GPIO_INT elink_cb_gpio_int_write
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define OFFSETOF(_s, _m) ((u32) ((u8 *)(&((_s *) 0)->_m) - \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_REV(_chip_id) ((_chip_id) & CHIP_REV_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E1(_chip_id) (CHIP_NUM(_chip_id) == \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E1X(_chip_id) ((CHIP_NUM(_chip_id) == \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E2(_chip_id) ((CHIP_NUM(_chip_id) == \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_57711(_chip_id) (CHIP_NUM(_chip_id) == \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_57711E(_chip_id) (CHIP_NUM(_chip_id) == \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define DO_CHIP_IS_E3(_chip_family) ((_chip_family == 0x1630) || \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E3(_chip_id) (DO_CHIP_IS_E3(((CHIP_NUM(_chip_id)) & 0xfff0)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* For EMUL: Ax=0xE, Bx=0xC, Cx=0xA. For FPGA: Ax=0xF, Bx=0xD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E3B0(_p) (CHIP_IS_E3(_p) && \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CHIP_IS_E3A0(_p) (CHIP_IS_E3(_p) && \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_USES_WARPCORE(_chip_id) (CHIP_IS_E3(_chip_id))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define SHMEM2_RD(cb, shmem2_base, _field) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define SHMEM2_HAS(cb, shmem2_base, field) (shmem2_base && \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Shortcut definitions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* ETS defines*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/**********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* INTERFACE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/**********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CL22_WR_OVER_CL45(_cb, _phy, _bank, _addr, _val) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define CL22_RD_OVER_CL45(_cb, _phy, _bank, _addr, _val) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic int elink_check_half_open_conn(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic int elink_sfp_module_detection(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * elink_check_lfa - This function checks if link reinitialization is required,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * or link flap can be avoided.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @params: link parameters
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * condition code.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic int elink_check_lfa(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 link_status, cfg_idx, lfa_mask, cfg_size;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, additional_config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* NOTE: must be first condition checked -
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to verify DCC bit is cleared in any case!
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "No LFA due to DCC flap after clp exit\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, additional_config),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Verify that link is up */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_status = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* if loaded after BOOT from SAN, don't flap the link in any case and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * rely on link set by preboot driver
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Verify that loopback mode is not set */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Verify that MFW supports LFA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Compare Duplex */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Duplex mismatch %x vs. %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (saved_val & lfa_mask), (req_val & lfa_mask));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Compare Flow Control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, req_flow_ctrl));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Flow control mismatch %x vs. %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (saved_val & lfa_mask), (req_val & lfa_mask));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Compare Link Speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, req_line_speed));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Link speed mismatch %x vs. %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (saved_val & lfa_mask), (req_val & lfa_mask));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_speed_cap_mask = REG_RD(cb, params->lfa_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Speed Cap mismatch %x vs. %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, additional_config)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Flow Ctrl AN mismatch %x vs. %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_req_fc_auto_adv, params->req_fc_auto_adv);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi eee_status = REG_RD(cb, params->shmem2_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "EEE mismatch %x vs. %x\n", params->eee_mode,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* LFA conditions are met */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_get_epio(struct elink_dev *cb, u32 epio_pin, u32 *en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sanity check */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to get\n", epio_pin);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set this EPIO to output */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *en = (REG_RD(cb, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_epio(struct elink_dev *cb, u32 epio_pin, u32 en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sanity check */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to set\n", epio_pin);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting EPIO pin %d to %d\n", epio_pin, en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set this EPIO to output */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gp_output = REG_RD(cb, MCP_REG_MCPR_GP_OUTPUTS);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the value for this EPIO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_epio(cb, pin_cfg - PIN_CFG_EPIO0, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, gpio_num, (u8)val, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_get_epio(cb, pin_cfg - PIN_CFG_EPIO0, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* (!defined EXCLUDE_WARPCORE) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* ETS section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e2e3a0_disabled(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS disabled configuration*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "ETS E2E3 disabled configuration\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mapping between entry priority to client number (0,1,2 -debug and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 3bits client num.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * as strict. Bits 0,1,2 - debug and management entries, 3 -
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS0 entry, 4 - COS1 entry.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * bit4 bit3 bit2 bit1 bit0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MCP and debug are strict
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* defines which entries (clients) are subjected to WFQ arbitration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For strict priority entries defines the number of consecutive
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * slots for the highest priority.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mapping between the CREDIT_WEIGHT registers and actual client
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS mode disable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If ETS mode is enabled (there is no strict priority) defines a WFQ
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * weight for COS0/COS1.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Defines the number of consecutive slots for the strict priority */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Getting min_w_val will be set according to line speed .
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Calculate min_w_val.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If the link isn't up (static configuration for example ) The
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * link will be according to 20GBPS.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Getting credit upper bound form min_w_val.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_ets_get_credit_upper_bound(const u32 min_w_val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 credit_upper_bound = (u32)ELINK_MAXVAL((150 * min_w_val),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Set credit upper bound for NIG.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e3b0_set_credit_upper_bound_nig(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_get_credit_upper_bound(min_w_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Will return the NIG ETS registers to init values.Except
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* credit_upper_bound.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* That isn't used in this configuration (No WFQ is enabled) and will be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* configured acording to spec
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 min_w_val = elink_ets_get_min_w_val_nig(vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mapping between entry priority to client number (0,1,2 -debug and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * reset value or init tool
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For strict priority entries defines the number of consecutive
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * slots for the highest priority.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mapping between the CREDIT_WEIGHT registers and actual client
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*Port 1 has 6 COS*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*Port 0 has 9 COS*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * as strict. Bits 0,1,2 - debug and management entries, 3 -
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS0 entry, 4 - COS1 entry.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * bit4 bit3 bit2 bit1 bit0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MCP and debug are strict
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* defines which entries (clients) are subjected to WFQ arbitration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Please notice the register address are note continuous and a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * for here is note appropriate.In 2 port mode port0 only COS0-5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * are never used for WFQ
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Set credit upper bound for PBF.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e3b0_set_credit_upper_bound_pbf(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_get_credit_upper_bound(min_w_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * port mode port1 has COS0-2 that can be used for WFQ.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < max_cos; i++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Will return the PBF ETS registers to init values.Except
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* credit_upper_bound.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* That isn't used in this configuration (No WFQ is enabled) and will be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* configured acording to spec
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mapping between entry priority to client number 0 - COS0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * TODO_ETS - Should be done by reset value or init tool
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 0x688 (|011|0 10|00 1|000) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* (10 1|100 |011|0 10|00 1|000) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TODO_ETS - Should be done by reset value or init tool */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 0x688 (|011|0 10|00 1|000)*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * In 4 port mode port1 has COS0-2 that can be used for WFQ.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < max_cos; i++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* E3B0 disable will return basicly the values to init values.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_disabled the chip isn't E3B0\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Disable will return basicly the values to init values.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_disabled(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status_t elink_status = ELINK_STATUS_OK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((CHIP_IS_E2(params->chip_id)) || (CHIP_IS_E3A0(params->chip_id)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status = elink_ets_e3b0_disabled(params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_disabled - chip not supported\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Set the COS mappimg to SP and BW until this point all the COS are not
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* set as SP or BW.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_set_cos_bw(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Calculate the total BW.A value of 0 isn't legal.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_get_total_bw(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Calculate total BW requested */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!ets_params->cos[cos_idx].params.bw_params.bw) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config BW"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "was set to 0\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is to prevent a state when ramrods
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * can't be sent
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ets_params->cos[cos_idx].params.bw_params.bw
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ets_params->cos[cos_idx].params.bw_params.bw;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check total BW is valid */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_E3B0_config total BW shouldn't be 0\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_E3B0_config total BW should be 100\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* We can handle a case whre the BW isn't 100 this can happen
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * if the TC are joined.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Invalidate all the sp_pri_to_cos.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* according to sp_pri_to_cos.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "parameter Illegal strict priority\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "parameter There can't be two COS's with "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "the same strict pri\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Returns the correct value according to COS and priority in
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* the sp_pri_cli register.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u64 elink_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Returns the correct value according to COS and priority in the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* sp_pri_cli register for NIG.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u64 elink_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* MCP Dbg0 and dbg1 are always with higher strict pri*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Returns the correct value according to COS and priority in the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* sp_pri_cli register for PBF.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u64 elink_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* according to sp_pri_to_cos.(which COS has higher priority)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* MCP Dbg0 and dbg1 are always with higher strict pri*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set all the strict priority first */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < max_num_of_cos; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_sp_set_pri_cli_reg "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "invalid cos entry\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* COS is used remove it from bitmap.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_sp_set_pri_cli_reg "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "invalid There can't be two COS's with"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " the same strict pri\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set all the Non strict priority i= COS*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < max_num_of_cos; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check if COS was already used for SP */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* COS wasn't used for SP */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* COS is used remove it from bitmap.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "entries were set\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only 6 usable clients*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only 9 usable clients*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Configure the COS to ETS according to BW and SP settings.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_e3b0_config(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status_t elink_status = ELINK_STATUS_OK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_disabled the chip isn't E3B0\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((ets_params->num_of_cos > max_num_of_cos)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config the number of COS "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "isn't supported\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Prepare sp strict priority parameters*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Prepare BW parameters*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_E3B0_config get_total_bw failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Upper bound is set according to current link speed (min_w_val
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * should be the same for upper bound and COS credit val).
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The function also sets the BW in HW(not the mappin
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cb, cos_entry, min_w_val_nig, min_w_val_pbf,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ets_params->cos[cos_entry].params.bw_params.bw,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ets_params->cos[cos_entry].params.sp_params.pri,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_config cos state not valid\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_e3b0_config set cos bw failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set SP register (which COS has higher priority) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_ets_E3B0_config set_pri_cli_reg failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set client mapping of BW and strict */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_status = elink_ets_e3b0_cli_map(params, ets_params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config SP failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ets_bw_limit_common(const struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS disabled configuration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Defines which entries (clients) are subjected to WFQ arbitration
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * client numbers (WEIGHT_0 does not actually have to represent
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS mode enabled*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Defines the number of consecutive slots for the strict priority */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * entry, 4 - COS1 entry.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * bit4 bit3 bit2 bit1 bit0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MCP and debug are strict
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS disabled configuration*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Total BW can't be zero\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS disabled configuration*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "ETS enabled strict configuration\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * as strict. Bits 0,1,2 - debug and management entries,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 3 - COS0 entry, 4 - COS1 entry.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * bit4 bit3 bit2 bit1 bit0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MCP and debug are strict
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For strict priority entries defines the number of consecutive slots
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * for the highest priority.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* ETS mode disable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Defines the number of consecutive slots for the strict priority */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Defines the number of consecutive slots for the strict priority */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mapping between entry priority to client number (0,1,2 -debug and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 3bits client num.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* PFC section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_pfc_xmac(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* XMAC base adrr */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initialize pause and pfc registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No PFC support */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* RX flow control - Process pause frame in receive direction
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TX flow control - Send pause packet when buffer is full */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else {/* PFC support */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Write pause and PFC registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Write pause and PFC registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set MAC address for source TX Pause/PFC frames */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_emac_get_pfc_stat(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read pfc statistic */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "pfc statistic read from EMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PFC received frames */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pfc_frames_received[0] = val_xon + val_xoff;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PFC received sent */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Read pfc statistic*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read pfc statistic */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "About to read PFC stats from EMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_emac_get_pfc_stat(params, pfc_frames_sent,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ! BNX2X_UPSTREAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_mdio_clk(struct elink_dev *cb, u32 chip_id,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * (a value of 49==0x31) and make sure that the AUTO poll is off
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Changing emac_mode from 0x%x to 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_is_4_port_mode(struct elink_dev *cb)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check 4-port override enabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port4mode_ovwr_val = REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Return 4-port mode override value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Return 4-port mode from input pin */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return (u8)REG_RD(cb, MISC_REG_PORT4MODE_EN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_mdio_emac_per_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set mdio clock per phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_emac_init(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* reset and unreset the emac core */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* init emac - use read-modify-write */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* self clear reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "EMAC reset reg is %u\n", val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set mac address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH + 4, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_xumac_nig(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_umac_rxtx(struct elink_params *params, u8 en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, umac_base + UMAC_REG_COMMAND_CONFIG);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable RX and TX */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_umac_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset UMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This register opens the gate for the UMAC despite its name */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid speed for UMAC %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure UMAC for EEE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "configured UMAC for EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable RX and TX */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Remove SW Reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check loopback mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * length used by the MAC receive logic to check frames.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Define the XMAC mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_xmac_init(struct elink_params *params, u32 max_speed)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 is_port4mode = elink_is_4_port_mode(cb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In 4-port mode, need to set the mode only once, so if XMAC is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * already out of reset, it means the mode has already been set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * and it must not* reset the XMAC again, since it controls both
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * ports of the path
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((CHIP_NUM(params->chip_id) == CHIP_NUM_57840_4_10) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_2_20) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_OBSOLETE)) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "XMAC already out of reset in 4-port mode\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Hard reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Init XMAC to 2 ports x 10G per path\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the number of ports on the system side to up to 2 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the number of ports on the Warp Core to 10G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the number of ports on the system side to 1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Init XMAC to 10G x 1 port per path\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the number of ports on the Warp Core to 10G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Init XMAC to 20G x 2 ports per path\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the number of ports on the Warp Core to 20G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Soft reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_xmac_rxtx(struct elink_params *params, u8 en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Send an indication to change the state in the NIG back to XON
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Clearing this bit enables the next set of this bit to get
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * rising edge
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pfc_ctrl = REG_RD(cb, xmac_base + XMAC_REG_PFC_CTRL_HI);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Disable XMAC on port %x\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, xmac_base + XMAC_REG_CTRL);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_xmac_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This register determines on which events the MAC will assert
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * error on the i/f to the NIG along w/ EOP.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This register tells the NIG whether to send traffic to UMAC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* When XMAC is in XLGMII mode, disable sending idles for fault
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Max packet size */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* CRC append for Tx packets */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* update PFC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting XMAC for EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable TX and RX */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set MAC in XLGMII mode for dual-mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->line_speed == ELINK_SPEED_20000) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check loopback mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_emac_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable BMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* enable emac and not bmac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* for paladium */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Use lane 1 (of lanes 0-3) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* for fpga */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Use lane 1 (of lanes 0-3) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_emac_enable: Setting FPGA\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* select the master lanes (out of 0-3) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* select XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* SerDes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* select SerDes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, emac_base + EMAC_REG_EMAC_RX_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* config GMII mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* ASIC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_RX_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* KEEP_VLAN_TAG, promiscuous */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, emac_base + EMAC_REG_EMAC_RX_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Setting this bit causes MAC control frames (except for pause
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * frames) to be passed on for processing. This setting has no
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * affect on the operation of the pause frames. This bit effects
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * all packets regardless of RX Parser packet sorting logic.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Turn the PFC off to make sure we are in Xon state before
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * enabling it.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable PFC again */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Loopback */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable emac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable emac for jumbo packets */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Strip CRC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable the NIG in/out to the bmac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable the NIG in/out to the emac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Take the BigMac out of reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable access for bmac registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_EMUL */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //EXCLUDE_EMAC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_pfc_bmac1(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable BigMAC to react on received Pause packets */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TX control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BMAC1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_pfc_bmac2(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set rx control: Strip CRC and enable BigMAC to relay
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * control packets to the system as well
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable BigMAC to react on received Pause packets */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Tx control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable PFC RX & TX & STATS and set 8 COS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] |= (1<<2); /* Force initial Xon */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear the force Xon */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable PFC RX & TX & STATS and set 8 COS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Time (based unit is 512 bit time) between automatic
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * re-sending of PP packets amd enable automatic re-send of
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Per-Priroity Packet as long as pp_gen is asserted and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * pp_disable is low.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= (1<<16); /* enable automatic re-send */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mac control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enable bmac loopback\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* When PFC enabled, Pass pause frames towards the NIG. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BMAC2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_pfc_nig_rx_priority_mask(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_mng(struct elink_params *params, u32 link_status)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_mb[params->port].link_status), link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_pfc_nig(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_nig_brb_pfc_port_params *nig_params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi int set_pfc = params->feature_config_flags &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "updating pfc nig parameters\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MAC control frames (that are not pause packets)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * will be forwarded to the XCM.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xcm_mask = REG_RD(cb, port ? NIG_REG_LLH1_XCM_MASK :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* NIG params will override non PFC params, since it's possible to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * do transition from PFC to SAFC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else /* Default non PFC mode - PAUSE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Output enable for RX_XCM # IF */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW PFC TX enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi nig_params->rx_cos_priority_mask[i], port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_update_pfc(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_nig_brb_pfc_port_params *pfc_params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The PFC and pause are orthogonal to one another, meaning when
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * PFC is enabled, the pause are disabled, and when PFC is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * disabled, pause are set according to the pause result.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_PFC_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update NIG params */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_pfc_nig(params, vars, pfc_params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "About to update PFC in BMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "About to update PFC in EMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_pfc_bmac2(params, vars, bmac_loopback);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_bmac1_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* XGXS control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TX MAC SA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ((params->mac_addr[2] << 24) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* MAC control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enable bmac loopback\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set rx mtu */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set tx mtu */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set cnt max size */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure SAFC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fix for emulation */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_EMUL */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BMAC1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_bmac2_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TX MAC SA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ((params->mac_addr[2] << 24) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure SAFC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set RX MTU */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set TX MTU */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set cnt max size */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_pfc_bmac2(params, vars, is_lb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BMAC2 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_bmac_enable(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset and unreset the BigMac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable access for bmac registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable BMAC according to BMAC type*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_bmac2_enable(params, vars, is_lb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_bmac1_enable(params, vars, is_lb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_bmac_rx(struct elink_dev *cb, u32 chip_id, u8 port, u8 en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 nig_bmac_enable = REG_RD(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only if the bmac is out of reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear Rx Enable bit in BMAC_CONTROL register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_pbf_update(struct elink_params *params, u32 flow_ctrl,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for init credit */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi init_crd = REG_RD(cb, PBF_REG_P0_INIT_CRD + port*4);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "BUG! init_crd 0x%x != crd 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update threshold */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update init credit */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update threshold */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update init credit */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "PBF updated to speed %d credit %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Probe the credit changes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * elink_get_emac_base - retrive emac base address
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @bp: driver handle
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @mdc_mdio_access: access type
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @port: port id
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * This function selects the MDC/MDIO access (through emac0 or
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * emac1) depend on the mdc_mdio_access, port, port swapped. Each
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * phy has a default access mode, which could also be overridden
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * by nvram configuration. This parameter, whether this is the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * default phy configuration, or the nvram overrun
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * configuration, is passed here as mdc_mdio_access and selects
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the emac_base for the CL45 read/writes operations
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_get_emac_base(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* CL22 access functions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_cl22_write(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Switch to CL22 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tmp = ((phy->addr << 21) | (reg << 16) | val |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "write phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_cl22_read(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Switch to CL22 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "read phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_NON_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* CL45 access functions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_cl45_read(struct elink_dev *cb, struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = ((phy->addr << 21) | (devad << 16) | reg |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "read phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "read phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Work around for E3 A0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, devad, 0xf, &temp_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_cl45_write(struct elink_dev *cb, struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tmp = ((phy->addr << 21) | (devad << 16) | reg |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "write phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tmp = ((phy->addr << 21) | (devad << 16) | val |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 50; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "write phy register failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Work around for E3 A0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, devad, 0xf, &temp_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* EEE section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_eee_has_cap(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem2_region, eee_status[params->port]))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_eee_calc_timer(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* time value in eee_mode --> used directly*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* hsi value in eee_mode --> time */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_eee_nvram_to_time(params->eee_mode &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* hsi values in nvram --> time*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi eee_mode = ((REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_set_timers(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Error: Tx LPI is enabled with timer 0\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* eee_idle in 1u --> eee_status in 16u */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_initial_config(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Propogate params' bits --> vars (for migration exposure) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_disable(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Make Certain LPI is disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_eee_advertise(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mask events preventing LPI generation */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertise 10GBase-T EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertise 1GBase-T EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_mng_eee(struct elink_params *params, u32 eee_status)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_eee_an_resolve(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "EEE negotiated - 100M\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "EEE negotiated - 1G\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "EEE negotiated - 10G\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BSC access functions from E3 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_bsc_module_sel(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read I2C output PINs */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi board_cfg = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read I2C output value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_cmn_pin_cfg));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting BSC switch\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_cfg_pin(cb, i2c_pins[idx], i2c_val[idx]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_bsc_read(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "invalid xfer_cnt %d. Max is 16 bytes\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable the engine */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Program slave device ID */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Start xfer with 0 byte to update the address pointer ???*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Poll for completion */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (i++ > 1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "wr 0 byte timed out after %d try\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Start xfer with read op */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Poll for completion */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (i++ > 1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "rd op timed out after %d try\n", i);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi data_array[i] = REG_RD(cb, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_NON_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_NON_COMMON_INIT) || defined(INCLUDE_WARPCORE_UC_LOAD)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_cl45_read_or_write(struct elink_dev *cb, struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, devad, reg, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, devad, reg, val | or_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_cl45_read_and_write(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, devad, reg, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, devad, reg, val & and_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Probe for the phy according to the given phy_addr, and execute
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the read request on it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[phy_index].addr == phy_addr) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Probe for the phy according to the given phy_addr, and execute
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the write request on it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[phy_index].addr == phy_addr) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if (!defined EXCLUDE_NON_COMMON_INIT) || (!defined EXCLUDE_WARPCORE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_get_warpcore_lane(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Figure out path swap value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi path_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi path_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Figure out port swap value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* Two port mode - no port swap */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Figure out path swap value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_aer_mmd(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (ELINK_USES_WARPCORE(params->chip_id)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi aer_val = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In Dual-lane mode, two lanes are joined together,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * so in order to configure them, the AER broadcast method is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 0x200 is the broadcast address for lanes 0,1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 0x201 is the broadcast address for lanes 2,3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Internal phy section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_serdes_access(struct elink_dev *cb, u8 port)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Clause 22 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Clause 45 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_serdes_deassert(struct elink_dev *cb, u8 port)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_serdes_deassert\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val = ELINK_SERDES_RESET_BITS << (port*16);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset and unreset the SerDes/XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_SERDES */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_xgxs_specific_func(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set correct devad */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_xgxs_deassert(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_xgxs_deassert\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset and unreset the SerDes/XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Resolve pause mode and advertisement Please refer to Table
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 28B-3 of the 802.3ab-1999 spec
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "ieee_fc = 0x%x\n", *ieee_fc);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_NON_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void set_phy_vars(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 actual_phy_idx, phy_index, link_cfg_idx;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 phy_config_swapped = params->multi_phy_config &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[actual_phy_idx].req_flow_ctrl =
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[actual_phy_idx].req_line_speed =
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[actual_phy_idx].speed_cap_mask =
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->req_line_speed[link_cfg_idx] ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "req_flow_ctrl %x, req_line_speed %x,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " speed_cap_mask %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[actual_phy_idx].req_line_speed,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[actual_phy_idx].speed_cap_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ext_phy_set_pause(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read modify write pause advertizing */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Ext phy AN advertize 0x%x\n", val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_pause_resolve(struct elink_vars *vars, u32 pause_result)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi switch (pause_result) { /* ASYM P ASYM P */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Ext PHY pause result 0x%x\n", pause_result);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_ext_phy_resolve_fc(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update the advertised flow-controled of LD/LP in AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_update_adv_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* But set the flow-control result as the requested one */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_update_adv_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Warpcore section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* The init_internal_warpcore should mirror the xgxs,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * i.e. reset the lane (if needed), set aer for the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * init configuration, and set/clear SGMII flag. Internal
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * phy init is done purely in phy_init stage.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define WC_TX_DRIVER(post2, idriver, ipre) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_link_attr(struct elink_params *params, u32 link_attr)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 1 - Program the TX/RX alignment markers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 2 - Configure the NP registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Start KR2 work-around timer which handles BCM8073 link-parner */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_link_attr(params, params->link_attr_sync);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_disable_kr2(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 1 - Program the TX/RX alignment markers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_link_attr(params, params->link_attr_sync);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Configure WC for LPI pass through\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart autoneg on the leading lane only */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore AER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable Autoneg: re-enable it after adv is done. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enable Auto Negotiation for KR\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set to default registers that may be overriden by 10G force */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check adding advertisement for 1G KX */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable CL37 1G Parallel Detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, addr, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check adding advertisement for 10G KR */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable 10G Parallel Detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Transmit PMD settings */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure the next lane if dual mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Advertised speeds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Advertised and set FEC (Forward Error Correction) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable CL37 BAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].default_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Advertise pause */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_set_pause(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Over 1G - AN local device user page 1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_20000)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_enable_AN_KR2(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable Auto-Detect to support 1G over CL37 as well */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wc_lane_config = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Force cl48 sync_status LOW to avoid getting stuck in CL73
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * parallel-detect loop when CL73 and CL37 are enabled.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore Polarity settings in case it was run over by
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * previous link owner
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable Autoneg: only on the main lane */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_10G_KR(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable Autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Leave cl72 training enable, needed for KR */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Global registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable CL36 PCS Tx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore AER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set speed via PMA/PMD register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable encoded forced speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn TX scramble payload only the 64/66 scrambler */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn RX scramble payload only the 64/66 scrambler */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set and clear loopback to cause a reset to 64/66 decoder */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 misc1_val, tap_val, tx_driver_val, lane, val;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Hold rxSeqStart */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Hold tx_fifo_reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable CL73 AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable 100FX Enable and Auto-Detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable 100FX Idle detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Block address to Remote PHY & Clear forced_speed[5] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn off auto-detect & fiber mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set filter_force_link, disable_false_link and parallel_detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set XFI / SFI */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cfg_tap_val = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TAP values are controlled by nvram, if value there isn't 0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Transmit PMD settings */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable fiber mode, enable and invert sig_det */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_lpi_passthrough(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10G XFI Full Duplex */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Release tx_fifo_reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Release rxSeqStart */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set global registers, so set AER lane to 0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable sequencer */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_PMA_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn off CL73 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 20G KR2 force speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable sequencer (over lane 0) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_20G_DXGXS(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Rx0 anaRxControl1G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Rx2 anaRxControl1G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Serdes Digital Misc1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Serdes Digital4 Misc3 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Transmit PMD settings */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear XFI clock comp in non-10G single lane mode. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_lpi_passthrough(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* SGMII Autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Speed not supported: 0x%x\n", phy->req_line_speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "set SGMII force speed %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, " (readback) %x\n", val16);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* SGMII Slave mode and disable signal detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn off parallel detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Re-enable parallel detect */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable autodet */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_reset_lane(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Take lane out of reset after configuration is finished */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Clear SFI/XFI link settings registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_clear_regs(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set XFI clock comp as default. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_get_mod_abs_int_cfg(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_sfp_ctrl)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Should not happen. This function called upon interrupt
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * triggered by GPIO ( since EPIO can only generate interrupts
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * So if this function was called and none of the GPIOs was set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * it means the shit hit the fan.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "No cfg pin %x for module detect indication\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic int elink_is_sfp_module_plugged(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_get_mod_abs_int_cfg(cb, params->chip_id,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Call the handling function in case module is detected */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiint elink_warpcore_get_sigdet(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return (gp2_status_reg0 >> (8+lane)) & 0x1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_config_runtime(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi serdes_net_if = (REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].default_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Do we get link yet? */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 0x81d1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the lane to see if link comes up.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart Autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } /*params->rx_tx_asic_rst*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_config_sfi(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_clear_regs(phy, params, lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_10G_XFI(phy, params, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sfp_e3_set_transmitter(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_sfp_ctrl)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the !tx_en since this pin is DISABLE_TX_LASER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Setting WC TX to %d\n", tx_en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For 20G, the expected pin to be used is 3 pins after the current */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_cfg_pin(cb, cfg_pin + 3, tx_en ^ 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi serdes_net_if = (REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].default_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Begin Warpcore init, link_speed %d, "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "serdes_net_if = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((phy->req_line_speed == ELINK_SPEED_100) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_10)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting SGMII mode\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_clear_regs(phy, params, lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable KR Auto Neg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode != ELINK_LOOPBACK_EXT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_enable_AN_KR(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting KR 10G-Force\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_10G_KR(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_clear_regs(phy, params, lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_10G_XFI(phy, params, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Issue Module detection if module is plugged, or
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * enabled transmitter to avoid current leakage in case
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * no module is connected
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_is_sfp_module_plugged(phy, params))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed != ELINK_SPEED_20000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Speed not supported yet\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_20G_DXGXS(cb, phy, lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Issue Module detection */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_enable_AN_KR(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting KR 20G-Force\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_20G_force_KR2(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Unsupported Serdes Net Interface 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Take lane out of reset after configuration is finished */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_e3_set_transmitter(params, phy, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Global register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear loopback settings (if any) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10G & 20G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update those 1-copy registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable 1G MDIO (1-copy) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable CL36 PCS Tx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore AER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_warpcore_loopback(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting Warpcore loopback type %x, speed %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->loopback_mode, phy->req_line_speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed < ELINK_SPEED_10000 ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10/100/1000/20G-KR2 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update those 1-copy registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable 1G MDIO (1-copy) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 1G loopback based on lane (1-copy) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Switch back to 4-copy registers */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10G / 20G-DXGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifdef ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_powerdown_secondport_lanes(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Figure out path swap value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi path_swap_ovr = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi path_swap = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Find which lanes to power down according to path swap value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Go through lanes which should be powered down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 4; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //INCLUDE_WARPCORE_UC_LOAD
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * elink_warpcore_sequencer
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @param enable - sequencer
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * @return u32
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Before starting any of the specific speed/protocol flow,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * there's need disable the sequencer and once all
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * configurations are made the sequencer will be enabled again.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * That way it is guaranteed that improper link won't be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * established during the init phase.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_sequencer(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_lane_swap(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Rx Lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Tx Lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_lane_polarity(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set RX polarity on all lanes; flip and enable the flip. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set TX polarity on all lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (wc_lane_config & SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_reset_warpcore(struct elink_dev *cb)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Resetting Warpcore\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for(time = 0; time < ELINK_MDIO_ACCESS_TIMEOUT; time++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pll_lock = REG_RD(cb, MISC_REG_WC0_PLL_LOCK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Flush all TX fifo */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "BUG! WARPCORE is still in reset!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_quad_mode(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to set lanes 0..3 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (lane = 0; lane < WC_LANE_MAX; lane++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset Asic lane */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // This access is required only for version 0xd101 of the WC FW
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set on clock compensation in WC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set on clock compensation in WC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * For WC/B0 programming register 0x8104 to value 0x8091 insures
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * that clock comensation in cl48 modes is enabled during
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * multi-port modes, and disabled during single port modes.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_dual_mode(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (lane = 0; lane < WC_LANE_MAX; lane++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set on clock compensation in WC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * For WC/B0 programming register 0x8104 to value 0x8091 insures
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * that clock comensation in cl48 modes is enabled during
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * multi-port modes, and disabled during single port modes.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In dual port mode XFI compensation should be disabled by
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * setting 0x83C0[14:13] to 2'b00 for each port.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This access is required only for version 0xd101 of the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure both ports to 20G to enable clock working on both ports */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (lane = 0x200; lane <= 0x201; lane++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_DXGXS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_20G_DXGXS(cb, phy, lane);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_warpcore_load_uc(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable External memory access */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initialize ram memory prior to programming it */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for completion of memory initialization */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cnt = 0; cnt < ELINK_WC_UC_TIMEOUT; cnt++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_CRC, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Load Warpcore microcode for E3 and after */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn off read_for_cmd bit, check for FW setting this later. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cnt = 0; cnt < ELINK_WC_RDY_TIMEOUT_MSEC; cnt++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* INCLUDE_WARPCORE_UC_LOAD */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sync_link(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fall thru */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fall thru */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fall thru */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fall thru */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Anything 10 and over uses the bmac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* Link down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Indicate no mac active */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_link_status_update(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update PHY configuration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->loopback_mode != ELINK_LOOPBACK_EXT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status = REG_RD(cb, params->shmem2_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sync media type */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "media_types = 0x%x\n", media_types);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sync AEU offset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].aeu_int_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->aeu_int_mask = REG_RD(cb, sync_offset);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sync PFC status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_attr_sync = SHMEM2_RD(cb, params->shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "line_speed %x duplex %x flow_ctrl 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed, vars->duplex, vars->flow_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_master_ln(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the master_ln for AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_reset_unicore(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the unicore */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_SERDES */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for the reset to self clear */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The reset erased the previous bank value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "BUG! XGXS is still in reset!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_swap_lanes(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Each two bits represents a lane number:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * No swap is 0123 => 0x1b no need to enable the swap
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_parallel_detection(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable parallel detection of HiG */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_autoneg(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* CL37 Autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* CL37 Autoneg Enabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else /* CL37 Autoneg Disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable/Disable Autodetection */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable TetonII and BAM autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable BAM aneg Mode and TetonII aneg Mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* TetonII and BAM Autoneg Disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable Cl73 FSM status bits */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable BAM Station Manager*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Advertise CL73 link speeds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* CL73 Autoneg Enabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else /* CL73 Autoneg Disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Program SerDes, forced speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_program_serdes(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Program duplex, disable autoneg and sgmii*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Program speed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - needed only if the speed is greater than 1G (2.5G or 10G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clearing the speed value before setting the right speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!((vars->line_speed == ELINK_SPEED_1000) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set extended capabilities */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For AN, we are always publishing full duplex */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_restart_autoneg(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_restart_autoneg\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable and restart BAM/CL37 aneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_restart_autoneg mii_control before = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_initialize_sgmii_process(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In SGMII mode, the unicore is always slave */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set sgmii mode (and not fiber) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If forced speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set speed, disable autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* There is nothing to set for 10M */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Invalid speed for SGMII */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Setting the full duplex */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* AN mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable and restart AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Link management
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "1G parallel detect link on port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "10G parallel detect link on port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_update_adv_fc(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "pause_result CL73 0x%x\n", pause_result);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "pause_result CL37 0x%x\n", pause_result);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_flow_ctrl_resolve(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Resolve from gp_status in case of AN complete and not sgmii */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update the advertised flow-controled of LD/LP in AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_adv_fc(phy, params, vars, gp_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* But set the flow-control result as the requested one */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_direct_parallel_detect_used(phy, params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_adv_fc(phy, params, vars, gp_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "flow_ctrl 0x%x\n", vars->flow_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_check_fallback_to_cl37(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 rx_status, ustat_val, cl37_fsm_received;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "elink_check_fallback_to_cl37\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 1: Make sure signal is detected */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Signal is not detected. Restoring CL73."
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 2: Check CL73 state machine */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "CL73 state-machine is not stable. "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Step 3: Check CL37 Message Pages received to indicate LP
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * supports only CL37
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "No CL37 FSM were received. "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "misc_rx_status(0x8330) = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The combined cl37/cl73 fsm state information indicating that
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * we are connected to a device which does not support cl73, but
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * does support cl37 BAM. In this case we disable cl73 and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * restart cl37 auto-neg
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable CL73 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart CL37 autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Disabling CL73, and restarting CL37 autoneg\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_xgxs_an_resolve(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_direct_parallel_detect_used(phy, params))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "link speed unsupported gp_status 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "link speed unsupported gp_status 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* link_down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, " phy_link_up %x line_speed %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_link_settings_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read gp_status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_flow_ctrl_resolve(phy, params, vars, gp_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* Link_down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check signal is detected */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read LP advertised speeds*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_CL73_IEEEB1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_OVER_1G,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->duplex, vars->flow_ctrl, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read gp_status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "PCS RX link status = 0x%x-->0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "0x81d1 = 0x%x\n", gp_status1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check for either KR, 1G, or AN up. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check Autoneg complete */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check parallel detect used */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the TX FIFO to fix SGMII issue */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case of KR link down, start up the recovering procedure */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->duplex, vars->flow_ctrl, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_gmii_tx_driver(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read precomp */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bits [10:7] at lp_up2, positioned at [15:12] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Replace tx_driver bits [15:12] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_emac_program(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "setting link speed & duplex\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, GRCBASE_EMAC0 + port*0x400 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10G not valid for EMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_preemphasis(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_xgxs_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->loopback_mode == ELINK_LOOPBACK_XGXS));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Forced speed requested? */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->loopback_mode == ELINK_LOOPBACK_EXT)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Program speed and duplex */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* AN_mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* AN enabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_brcm_cl37_advertisement(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Program duplex & pause advertisement (for aneg) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_ieee_aneg_advertisement(phy, params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_autoneg(phy, params, vars, enable_cl73);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable and restart AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_restart_autoneg(phy, params, enable_cl73);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* SGMII mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_initialize_sgmii_process(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((phy->req_line_speed == ELINK_SPEED_100) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_10))) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the SerDes and wait for reset bit return low */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Setting the masterLn_def again after the reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u16 elink_wait_reset_complete(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for soft reset to get cleared up to 1 sec */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_link_int_enable(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Setting the status to report on link up for either XGXS or SerDes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enabled XGXS interrupt\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enabled external phy int\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* SerDes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enabled SerDes interrupt\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "enabled external phy int\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "port %x, is_xgxs %x, int_status 0x%x\n", port,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->switch_cfg == ELINK_SWITCH_CFG_10G),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_rearm_latch_signal(struct elink_dev *cb, u8 port,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable the MI INT ( external phy int ) by writing 1 to the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * status register. Link down indication is high-active-signal,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * so in this case we need to write the status to clear the XOR
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read Latched signals */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "latch_status = 0x%x\n", latch_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Handle only those with latched-signal=up.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For all latched-signal=up : Re-Arm Latch signals */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (latch_status & 0xfffe) | (latch_status & 1));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For all latched-signal=up,Write original_signal to status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_link_int_ack(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* First reset all status we assume only one line will be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * change at a time
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable the link interrupt by writing 1 to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the relevant lane in the status register
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Ack link up interrupt with mask 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(ELINK_EMUL_ONLY) && (!defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_format_ver(u32 num, u8 *str, u16 *len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need more than 10chars for this format */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8705
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Extract first external phy*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY1].ver_addr);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->num_phys == ELINK_MAX_PHYS) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY2].ver_addr);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_xgxs_loopback(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed != ELINK_SPEED_1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "XGXS 10G loopback enable\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Change the uni_phy_addr in the nig */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi md_devad = REG_RD(cb, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set aer mmd back */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* And md_devad */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "XGXS 1G loopback enable\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_set_led(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_vars *vars, u8 mode, u32 speed)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "elink_set_led: port %x, mode %d\n", port, mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "speed 0x%x, hw_led_mode 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For all other phys, OPER mode is same as ON, so in case
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * link is down, do nothing
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CHIP_IS_E2(params->chip_id) && params->num_phys == 2) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is a work-around for E2+8727 Configurations */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Return here without enabling traffic
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * LED blink and setting rate in ON mode.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * In oper mode, enabling LED blink
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * and setting rate is needed.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is a work-around for HW issue found when link
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is up in CL73
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((params->phy[ELINK_EXT_PHY1].type ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Break here; otherwise, it'll disable the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * intended override.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 nig_led_mode = ((params->hw_led_mode <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set blinking rate to ~15.9Hz */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For speeds less than 10G LED scheme is different */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "elink_set_led: Invalid led mode %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* This function comes to reflect the actual link state read DIRECTLY from the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_FPGA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_EMUL */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check 20G link */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check 10G link and below*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 lane = elink_get_warpcore_lane(int_phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link is up only if both local phy and external phy are up */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In XGXS loopback mode, do not check external PHY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No external PHY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi serdes_phy_type = ((params->phy[phy_index].media_type ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_link_initialize(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case of external phy existence, the line speed would be the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * line speed linked up by the external phy. In case it is direct
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * only, then the line_speed during initialization will be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * equal to the req_line_speed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initialize the internal phy in case this is a direct board
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * (no external phys), or this board has external phy which requires
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* init ext phy and enable link state int */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->loopback_mode == ELINK_LOOPBACK_XGXS));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_INT_PHY].config_init)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Re-read this value in case it was changed inside config_init due to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * limitations of optic module
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Init external phy*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_SERDES_LINK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No need to initialize second phy in case of first
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * phy only selection. In case of second phy, we do
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * need to initialize the first phy, since they are
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_SERDES_LINK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Not initializing second phy\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the interrupt indication after phy was initialized */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_int_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the SerDes/XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if (!defined ELINK_EMUL_ONLY) && ((!defined EXCLUDE_BCM87x6) || (!defined EXCLUDE_SFX7101) || (!defined EXCLUDE_BCM8705))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_common_ext_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "reset external PHY\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_LINK_RESET */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_update_link_down(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Port %x: Link is down\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Indicate no mac active */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Activate nig drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable emac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_bmac_rx(cb, params->chip_id, params->port, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Prevent LPI Generation by chip */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng_eee(params, vars->eee_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_update_link_up(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= (LINK_STATUS_LINK_UP |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (ELINK_USES_WARPCORE(params->chip_id)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Found errors on XMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling LPI assertion\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_bmac_enable(params, vars, 0, 1) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Found errors on BMAC\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* AN complete? */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PBF - link up */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc |= elink_pbf_update(params, vars->flow_ctrl,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng_eee(params, vars->eee_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check remote fault */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_check_half_open_conn(params, vars, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_chng_link_count(struct elink_params *params, u8 clear)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Verify the link_change_count is supported by the MFW */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(SHMEM2_HAS(cb, params->shmem2_base, link_change_count)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem2_region, link_change_count[params->port]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* The elink_link_update function should be called upon link
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Link is considered up as follows:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - SINGLE_MEDIA - The link between the 577xx and the external
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * phy (XGXS) need to up as well as the external link of the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * phy (PHY_EXT1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - DUAL_MEDIA - The link between the 577xx and the first
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * external phy needs to be up, and at least one of the 2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * external phy link must be up.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_vars phy_vars[ELINK_MAX_PHYS];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* different consideration, since vars holds inner state */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy_vars[phy_index].eee_status = vars->eee_status;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "port %x, XGXS?%x, int_status 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable emac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Check external link change only for external phys, and apply
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * priority selection between them in case the link on both phys
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is up. Note that instead of the common vars, a temporary
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * vars argument is used since each phy may have different link/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[phy_index];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read link status and params of this ext phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_link_up = phy->read_status(phy, params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "phy in index %d link is up\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "phy in index %d link is down\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In this option, the first PHY makes sure to pass the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * traffic through itself only.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Its not clear how to reset the link on the second phy
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In this option, the first PHY makes sure to pass the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * traffic through the second PHY.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link indication on both PHYs with the following cases
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is invalid:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - FIRST_PHY means that second phy wasn't initialized,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * hence its link is expected to be down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - SECOND_PHY means that first phy should not be able
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to link up by itself (using configuration)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * - DEFAULT should be overriden during initialiazation
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid link indication"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "mpc=0x%x. DISABLING LINK !!!\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Read the status of the internal phy. In case of
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * DIRECT_SINGLE_MEDIA board, this link is the external link,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * otherwise this is the link between the 577xx and the first
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * external phy
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_INT_PHY].read_status)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The INT_PHY flow control reside in the vars. This include the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * case where the speed or flow control are not set to AUTO.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Otherwise, the active external phy flow control result is set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to the vars. The ext_phy_line_speed is needed to check if the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * speed is different between the internal phy and external phy.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * This case may be result of intermediate link speed change.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link speed is taken from the XGXS. AN and FC result from
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the external phy.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= phy_vars[active_external_phy].link_status;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* if active_external_phy is first PHY and link is up - disable
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * disable TX on second external PHY
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (active_external_phy == ELINK_EXT_PHY1) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Disabling TX on EXT_PHY2\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[ELINK_EXT_PHY2].phy_specific_func(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->duplex = phy_vars[active_external_phy].duplex;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[active_external_phy].supported &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_SERDES_LINK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~LINK_STATUS_SERDES_LINK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status = phy_vars[active_external_phy].eee_status;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Active external phy selected: %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " ext_phy_line_speed = %d\n", vars->flow_ctrl,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Upon link speed change set the NIG into drain mode. Comes to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * deals with possible FIFO glitch due to clk change when speed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is decreased without link down indicator
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (ext_phy_line_speed != vars->line_speed)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Internal link speed %d is"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " different than the external"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (prev_line_speed != vars->line_speed) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Anything 10 and over uses the bmac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_link_int_ack(params, vars, link_10g_plus);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case external phy link is up, and internal link is down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * (not initialized yet probably after link initialization, it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * needs to be initialized.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Note that after link down-up as result of cable plug, the xgxs
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * link would probably become up again without the need
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * initialize it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "ext_phy_link_up = %d, int_link_up = %d,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi && ext_phy_link_up && !vars->phy_link_up) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_INT_PHY].config_init)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link is up only if both local phy and external phy (in case of
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * non-direct board) are up and no fault detected on active PHY.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy_vars[active_external_phy].fault_detected == 0));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update the PFC configuration in case it was changed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_PFC_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_update_link_up(params, vars, link_10g_plus);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update MCP link status was changed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_fw_command(cb, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/*****************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* External Phy section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/*****************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_save_spirom_version(struct elink_dev *cb, u8 port,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "FW version 0x%x:0x%x for port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (u16)(spirom_ver>>16), (u16)spirom_ver, port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if (!defined EXCLUDE_XGXS) && (!defined EXCLUDE_COMMON_INIT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_save_bcm_spirom_ver(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_spirom_version(cb, port, (u32)(fw_ver1<<16 | fw_ver2),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_XGXS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_ext_phy_10G_an_resolve(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* common BCM8073/BCM8727 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8073_resolve_fc(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_10 ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_ext_phy_resolve_fc(phy, params, vars) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Ext PHY CL37 pause result 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8073_8727_external_rom_boot(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Boot port from external ROM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* EDC grst */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Ucode reboot and rst */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset internal microprocessor */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Release srst bit */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Delay 100ms per the PHY specifications */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 8073 sometimes taking longer to download */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_8073_8727_external_rom_boot port %x:"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Download failed. fw version = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((fw_msgout & 0xff) != 0x03 && (phy->type ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear ser_boot_ctl bit */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "elink_8073_8727_external_rom_boot port %x:"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Download complete. fw version = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8073 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8073_is_snr_needed(struct elink_dev *cb, struct elink_phy *phy)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is only required for 8073A1, version 102 only */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read 8073 HW revision*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No need to workaround in 8073 A1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* SNR should be applied only for version 0x102 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8073_xaui_wa(struct elink_dev *cb, struct elink_phy *phy)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No need to workaround in 8073 A1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* XAUI workaround in 8073 A0: */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* After loading the boot ROM and restarting Autoneg, poll
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Dev1, Reg $C820:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If bit [14] = 0 or bit [13] = 0, continue on with
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * system initialization (XAUI work-around not required, as
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * these bits indicate 2.5G or 1G link up).
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(val & (1<<14)) || !(val & (1<<13))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "XAUI work-around not required\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * MSB (bit15) goes to 1 (indicating that the XAUI
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * workaround has completed), then continue on with
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * system initialization.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "XAUI workaround has completed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Warning: XAUI work-around timeout !!!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_807x_force_10G(struct elink_dev *cb, struct elink_phy *phy)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Force KR or KX */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8073_set_pause_cl37(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Ext phy AN advertize cl37 0x%x\n", cl37_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8073_specific_func(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable LASI */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8073_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore normal power mode*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8073_set_pause_cl37(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Swap polarity if required - Must be done only in non-1G mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure the 8073 to swap _P and _N of the KR lines */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Swapping polarity for the 8073\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 10G Rx/Tx and 1G Tx signal polarity swap */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable CL37 BAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].default_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Forced speed 10G on 807X\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (phy->req_line_speed == ELINK_SPEED_2500) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Note that 2.5G works only when used with 1G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * advertisement
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Note that 2.5G works only when used with 1G advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "807x autoneg val = 0x%x\n", val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_2500)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Allow 2.5G for A1 and above */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Add support for CL37 (passive mode) II */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Add support for CL37 (passive mode) III */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The SNR will improve about 2db by changing BW and FEE main
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * tap. Rest commands are executed after link is up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Change FFE main cursor to 5 in EDC register
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable FEC (Forware Error Correction) Request in the AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_set_pause(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8073_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8703 LASI status 0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear the interrupt LASI status register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "807x PCS status 0x%x->0x%x\n", val2, val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear MSG-OUT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check the LASI */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "KR 0x9003 0x%x\n", val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check the link status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "KR PCS status 0x%x\n", val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "PMA_REG_STATUS=0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((phy->req_line_speed != ELINK_SPEED_10000))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check the link status on 1.1.2 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "KR PMA status 0x%x->0x%x,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "an_link_status=0x%x\n", val2, val1, an1000_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (link_up && elink_8073_is_snr_needed(cb, phy)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The SNR will improve about 2dbby changing the BW and FEE main
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * tap. The 1st write to change FFE main tap is set before
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * restart AN. Change PLL Bandwidth in EDC register
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Change CDR Bandwidth in EDC register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link up in 2.5G\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link is down\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Swap polarity if required */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure the 8073 to swap P and N of the KR lines */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set bit 3 to invert Rx in 1G mode and clear this bit
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * when it`s in 10G mode.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Swapping 1G polarity for"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "the 8073\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_10G_an_resolve(cb, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8073_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Setting 8073 port %d into low power mode\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8705 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8705_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore normal power mode*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* BCM8705 doesn't have microcode, hence the 0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_spirom_version(cb, params->port, params->shmem_base, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8705_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8705 1.c809 val=0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8705 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* SFP+ module Section */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_disable_pmd_transmit(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable transmitter only for bootcodes which can enable it afterwards
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * (for D3 link)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Disabling PMD transmitter\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "NOT disabling PMD transmitter\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling PMD transmitter\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_get_gpio_port(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return gpio_port ^ (swap_val && swap_override);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_en_mode = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "Setting transmitter tx_en=%x for port %x "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sfp_set_transmitter(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Setting SFP+ transmitter to %d\n", tx_en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_e3_set_transmitter(params, phy, tx_en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Reading from eeprom is limited to 0xf\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the read command byte count */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the read command address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Activate read command */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait up to 500us for command complete status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 100; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Got bad status 0x%x when reading from SFP+ EEPROM\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read the buffer */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < byte_cnt; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 100; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM87x6
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_power_module(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting SFP+ module power to %d using pin cfg %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Low ==> corresponding SFP+ module is powered
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * high ==> the SFP+ module is powered down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Reading from eeprom is limited to 16 bytes\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 4 byte aligned address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Note that 100us are not enough here */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_bsc_read(params, cb, dev_addr, addr32, 0, byte_cnt,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Reading from eeprom is limited to 0xf\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 2-wire transfer rate of SFP+ module EEPROM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to 100Khz since some DACs(direct attached cables) do
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * not work at 400Khz.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to read from 1.8000 to clear it */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the read command byte count */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the read command address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the destination address */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Activate read command */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait appropriate time for two-wire command to finish before
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * polling the status register
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait up to 500us for command complete status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 100; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Got bad status 0x%x when reading from SFP+ EEPROM\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read the buffer */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < byte_cnt; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 100; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_NON_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE; i++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (checksum == sfp_a2_buf[ELINK_SFP_EEPROM_A2_CC_DMI_ADDR])
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "invalid dev_addr 0x%x\n", dev_addr);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi read_func = elink_8726_read_sfp_module_eeprom;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi read_func = elink_8727_read_sfp_module_eeprom;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi read_func = elink_warpcore_read_sfp_module_eeprom;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = read_func(phy, params, dev_addr, addr, xfer_size,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_get_edc_mode(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* First check for copper cable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_link_attr(params, params->link_attr_sync);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check if its active cable (includes SFP+ module)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * of passive cable
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Active Copper cable detected\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Even in case PASSIVE_DAC indication is not set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * treat it as a passive DAC cable, since some cables
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * don't have this indication.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Passive Copper cable detected\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Unknown copper-cable-type\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Module is considered as 1G in case it's NOT compliant with
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * any 10G ethernet protocol.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "1G SFP module detected\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed != ELINK_SPEED_1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Current SFP module in port %d is not"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " compliant with 10G Ethernet\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Some 1G-baseT modules will not link up,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * unless TX_EN is toggled with long delay in
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "10G Optic module detected\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->req_line_speed = params->req_line_speed[cfg_idx];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Unable to determine module type 0x%x !!!\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].media_type);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update media type for non-PMF sync */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Failed to read Option field from module EEPROM\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "EDC mode is set to 0x%x\n", *edc_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* This function read the relevant field from the module (SFP+), and verify it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is compliant with this board
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_feature_config[params->port].config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "NOT enforcing module verification\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Use specific phy request */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Use first phy request only in case of non-dual media*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "FW does not support OPT MDL verification\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No support in OPT MDL detection */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "FW does not support OPT MDL verification\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi fw_resp = elink_cb_fw_command(cb, cmd, fw_cmd_param);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Format the warning message */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Port %d from %s part number %s\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initialization time after hot-plug may take up to 300ms for
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * some phys type ( e.g. JDSU )
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (timeout = 0; timeout < 60; timeout++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_warpcore_read_sfp_module_eeprom(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_read_sfp_module_eeprom(phy, params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "SFP+ module initialization took %d ms\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_power_module(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Make sure GPIOs are not using for LED mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In the GPIO register, bit 4 is use to determine if the GPIOs are
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * where the 1st bit is the over-current(only input), and 2nd bit is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * for power( only output )
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * In case of NOC feature is disabled and power is up, set GPIO control
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * as input to enable listening of over-current indication
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set GPIO control to OUTPUT, and set the power bit
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to according to the is_power_up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8726_set_limiting_mode(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Current Limiting mode is 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting LIMITING MODE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* LRM mode ( default )*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Changing to LRM mode takes quite few seconds. So do it only
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * if current mode is limiting (default is LRM)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8727_set_limiting_mode(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_specific_func(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Make MOD_ABS give interrupt on change */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * status which reflect SFP+ module over-current
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Function 0x%x not supported by 8727\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_e1e2_module_fault_led(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 fault_led_gpio = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].sfp_ctrl)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_port = elink_get_gpio_port(params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "Set fault module-detected led "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "pin %x port %x mode %x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Error: Invalid fault led mode 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifdef ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_e3_module_fault_led(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_sfp_ctrl)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting Fault LED to %d using pin cfg %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_sfp_module_fault_led(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Setting SFP+ module fault LED to %d\n", gpio_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Low ==> if SFP+ module is supported otherwise
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * High ==> if SFP+ module is not on the approved vendor list
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_e3_module_fault_led(params, gpio_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_e1e2_module_fault_led(params, gpio_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifdef ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_hw_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Put Warpcore in low power mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Put LCPLL in low power mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_power_sfp_module(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_DEBUG */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Setting SFP+ power to %x\n", power);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8727_power_module(params->cb, phy, power);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_power_module(params, power);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_warpcore_set_limiting_mode(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is a global register which controls all lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* A must read */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart microcode to re-read the new mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_set_limiting_mode(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8726_set_limiting_mode(params->cb, phy, edc_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8727_set_limiting_mode(params->cb, phy, edc_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_limiting_mode(params, phy, edc_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_sfp_module_detection(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_feature_config[params->port].config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enabled transmitter by default */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "SFP+ module plugged in/out detected on port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Power up module */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to get valid module type\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (elink_verify_sfp_module(phy, params) != 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check SFP+ module compatibility */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Module verification failed!!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn on fault module-detected led */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check if need to power down the SFP+ module */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Shutdown SFP+ module!!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Turn off fault module-detected led */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check and set limiting mode / LRM mode on 8726. On 8727 it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * is done automatically
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_limiting_mode(params, phy, edc_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable transmit for this module if the module is not approved, and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * laser needs to be disabled.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((rc != 0) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_handle_module_detect_int(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Always enable TX laser,will be disabled in case of fault */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_get_mod_abs_int_cfg(cb, params->chip_id, params->shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to get MOD_ABS interrupt config\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set valid module led off */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Get current gpio val reflecting module plugged in / out*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Call the handling function in case module is detected */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->flags |= ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case WC is out of reset, reconfigure the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * link speed while taking into account 1G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * module limitation.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->flags &= ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Module was plugged out.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Disable transmit for this module
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Used by 8706 and 8727 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sfp_mask_fault(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Mask or enable the fault event. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* common BCM8706/BCM8726 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8706_8726_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear RX Alarm*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear LASI indication*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " link_status 0x%x\n", rx_sd, pcs_status, val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * are set, or if the autoneg bit 1 is set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Capture 10G link fault. Read twice to clear stale value. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8706 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8706_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait until fw is loaded */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "XGXS 8706 is initialized after %d ms\n", cnt);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 4; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear first 3 bits of the control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set control bits according to configuration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting RX Equalizer to BCM8706"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Force speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "XGXS 8706 force 10Gbps\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Arm LASI for link and Tx fault. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Force 1Gbps using autoneg with 1G advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Allow CL37 through CL73 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable Full-Duplex advertisement on CL37 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable CL37 AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 1G support */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable clause 73 AN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_bcm_spirom_ver(cb, phy, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * power mode, if TX Laser is disabled
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_en_mode = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].sfp_ctrl))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8706_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_8706_8726_read_status(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8726 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8726_config_loopback(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "PMA/PMD ext_phy_loopback: 8726\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8726_external_rom_boot(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to wait 100ms after reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Micro controller re-boot */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set soft reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for 150ms for microcode load */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_bcm_spirom_ver(cb, phy, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8726_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 link_up = elink_8706_8726_read_status(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8726_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Initializing BCM8726\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to call module detected on initialization since the module
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * detection triggered by actual module insertion might occur before
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * driver is loaded, and when driver is loaded, it reset all
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * registers, including the transmitter
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting 1G clause37\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set Flow control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_set_pause(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable RX-ALARM control to receive interrupt for 1G speed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* Default 10G. Set only LASI control */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set TX PreEmphasis if needed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8726_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "elink_8726_link_reset port %d\n", params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set serial boot control for external load */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8727 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_set_link_led(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only NOC flavor requires to set the LED specifically */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_hw_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The PHY reset is controlled by GPIO 1. Fake the port number
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to cancel the swap done in set_gpio()
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_config_speed(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set option 1G speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->req_line_speed == ELINK_SPEED_1000) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Power down the XAUI until link is up in case of dual-media
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting 1G clause37\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Since the 8727 has only single reset pin, need to set the 10G
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * registers although it is default
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8727_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Initializing BCM8727\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initially configure MOD_ABS to interrupt when module is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * presence( bit 8)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * When the EDC is off it locks onto a reference clock and avoids
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * becoming 'lost'
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable/Disable PHY transmitter output */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_disable_pmd_transmit(params, phy, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set TX PreEmphasis if needed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * power mode, if TX Laser is disabled
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi tx_en_mode = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].sfp_ctrl))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_handle_mod_abs(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Module is absent */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "MOD_ABS indication show module is absent\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 1. Set mod_abs to detect next module
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * presence event
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2. Set EDC off by setting OPTXLOS signal input to low
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * When the EDC is off it locks onto a reference clock and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * avoids becoming 'lost'.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear RX alarm since it stays up as long as
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the mod_abs wasn't changed
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Module is present */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "MOD_ABS indication show module is present\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* First disable transmitter, and if the module is ok, the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * module_detection will enable it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 1. Set mod_abs to detect next module absent event ( bit 8)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2. Restore the default polarity of the OPRXLOS signal and
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * this signal will then correctly indicate the presence or
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * absence of the Rx signal. (bit 9)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear RX alarm since it stays up as long as the mod_abs
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * wasn't changed. This is need to be done before calling the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * module detection, otherwise it will clear* the link update
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reconfigure link speed based on module type limitations */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No need to check link status in case of module plugged in/out */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_8727_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If PHY is not initialized, do not check link status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check the LASI on Rx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "8727 LASI status 0x%x\n", val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear MSG-OUT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If a module is present and there is need to check
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * for over current
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check over-current using 8727 GPIO0 input*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi oc_port = PATH_ID(cb) + (params->port << 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "8727 Power fault has been detected on port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "been detected and the power to "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "that SFP+ module has been removed "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "to prevent failure of the card. "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "Please remove the SFP+ module and "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "restart the system to clear this "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "error.\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable all RX_ALARMs except for mod_abs */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for module_absent_event */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear RX alarm */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8727_power_module(params->cb, phy, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } /* Over current check */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* When module absent bit is set, check module */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable all mod_abs and link detection bits */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling 8727 TX laser\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bits 0..2 --> speed detected,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Bits 13..15--> link is down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "port %x: External link is down\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Capture 10G link fault. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed == ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "duplex = 0x%x\n", vars->duplex);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_1000)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case of dual-media board and 1G, power up the XAUI side,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * otherwise power it down. For 10G it is done automatically
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8727_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable/Disable PHY transmitter output */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_disable_pmd_transmit(params, phy, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable Transmitter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear LASI */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM8481/BCM84823/BCM84833 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_save_848xx_spirom_version(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_spirom_version(cb, port, fw_ver1 & 0xfff,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "phy fw version(1)\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Unable to read 848xx phy fw "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "version(2)\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* lower 16 bits of the register SPI_FW_STATUS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* upper 16 bits of register SPI_FW_STATUS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_spirom_version(cb, port, (fw_ver2<<16) | fw_ver1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8481 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_848xx_set_led(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PHYC_CTL_LED_CTL */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* stretch_en for LED3*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_848xx_specific_func(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Save spirom version */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_848xx_spirom_version(phy, cb, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This phy uses the NIG latch mechanism since link indication
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * arrives through its LED4 and not via its LASI signal, so we
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * get steady signal instead of clear on read
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_en(cb, NIG_REG_LATCH_BC_0 + params->port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 autoneg_val, an_1000_val, an_10_100_val;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set 1000 speed advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_set_pause(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable forced speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_1000)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 10/100 speed advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable autoneg and restart autoneg for legacy speeds
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable autoneg and restart autoneg for legacy speeds
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only 10/100 are allowed to work in FORCE mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->req_line_speed == ELINK_SPEED_100) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enabled AUTO-MDIX when autoneg is disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The PHY needs this set even for forced link. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting 100M force\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->req_line_speed == ELINK_SPEED_10) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enabled AUTO-MDIX when autoneg is disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Always write this if this is not 84833/4.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * For 84833/4, write it only when it's a forced speed.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_10000)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart autoneg for 10G*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8481_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore normal power mode*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_848xx_cmn_config_init(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8481
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Write CMD_OPEN_OVERRIDE to STATUS reg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "FW cmd: FW not ready.\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Prepare argument(s) and issue command */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Gather returning data */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check for configuration. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi pair_swap = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only the second argument is used for this command */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Pairswap OK, val=0x%x\n", data[1]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_84833_get_reset_gpios(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Assume that these will be GPIOs, not EPIOs. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Map config param to register bit. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[0].e3_cmn_pin_cfg));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* E2, look from diff place of shmem. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 other_shmem_base_addr = REG_RD(cb, params->shmem2_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Work around for 84833 LED failure inside RESET status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi shmem_base_path[1] = other_shmem_base_addr;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "84833 hw reset on pin values 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EDEBUG
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_BCM84833
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Don't Advertise 10GBase-T EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Prevent Phy from working in EEE and advertising it */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "EEE disable failed.\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_eee_disable(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "EEE enable failed.\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_848x3_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM84833
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* MDIO reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for GPHY to come out of reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM84833
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* BCM84823 requires that XGXS links up first @ 10G for normal
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_BCM8481
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* Set dual-media configuration according to configuration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi actual_phy_selection = elink_phy_selection(params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Do nothing. Essentially this is like the priority copper */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Do nothing here. The first PHY won't be initialized at all */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "Multi_phy config = 0x%x, Media control = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_84833_pair_swap_cfg(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Keep AutogrEEEn disabled. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Cfg AutogrEEEn failed.\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_BCM84833
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_848xx_cmn_config_init(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_848xx_spirom_version(phy, cb, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* 84833 PHY has a better feature and doesn't need to support this. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 cms_enable = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].default_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8481 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure EEE support */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_8483x_disable_eee(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_8483x_enable_eee(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_8483x_disable_eee(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to set EEE advertisement\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Bring PHY out of super isolate mode as the final step. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM84833 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_848xx_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check 10G-BaseT link status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check PMD signal ok */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check link 10G */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_10G_an_resolve(cb, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else { /* Check Legacy speed link */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable expansion register 0x42 (Operation mode status) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Get legacy speed operation status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Legacy speed status = 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_up = ((legacy_status & (1<<11)) == (1<<11));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else { /* Should not happen: Treat as link down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* For IEEE testing, check for a fake link. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Link is up in %dMbps, is_duplex_full= %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check legacy speed AN resolution */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "BCM848x3: link speed is %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read LP advertised speeds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if (!defined EXCLUDE_BCM84833) && (!defined EXCLUDE_WARPCORE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Determine if EEE was negotiated */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi status = elink_format_ver(spirom_ver, str, len);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8481_hw_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_8481_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_8481
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_848x3_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_848xx_set_link_led(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OFF\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set LED masks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set LED masks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable MI_INT interrupt before setting LED4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * source to constant off.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE ON\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set control reg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set LED masks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable MI_INT interrupt before setting LED4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * source to constant on.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OPER\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set control reg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting LINK_SIGNAL\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set LED masks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * sources are all wired through LED1, rather than only
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 10G in other modes.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Tell LED3 to blink on source */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore LED4 source to external link,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * and re-enable interrupts.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This is a workaround for E3+84833 until autoneg
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * restart is fixed in f/w
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8481 / EXCLUDE_BCM8481 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* 54618SE PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic int elink_54618se_init_required(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 autoneg_val, an_1000_val, an_10_100_val, ctrl, legacy_status;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* read all advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case PHY is in reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check conditions to avoid link reset in case link was
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * already initialized and up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_54618se_specific_func(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure LED4: set to INTR (0x6). */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Accessing shadow register 0xe. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Configure INTR based on link status change. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_54618se_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!elink_54618se_init_required(phy, params))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This works with E3 only, no need to check the chip
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * before determining the port.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Drive pin high to bring the GPHY out of reset. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* wait for GPHY to reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* reset phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for GPHY to reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } // If init required
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set up fc */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read all advertisement */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable forced speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->req_line_speed == ELINK_SPEED_1000)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Advertise 10/100 link speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only 10/100 are allowed to work in FORCE mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_100) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enabled AUTO-MDIX when autoneg is disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting 100M force\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->req_line_speed == ELINK_SPEED_10) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enabled AUTO-MDIX when autoneg is disabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl22_read(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to advertise EEE only when requested,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * and either no LPI assertion was requested,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * or it was requested and a valid timer was set.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Also notice full duplex is required for EEE.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Don't Advertise 1GBase-T EEE\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Handle legacy auto-grEEEn */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Enabling Auto-GrEEEn\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_5461x_set_link_led(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "54618x set link led (mode=%x)\n", mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_54618se_link_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!elink_54618se_init_required(phy, params))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case of no EPIO routed to reset the GPHY, put it
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * in low power mode.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl22_write(cb, phy, MDIO_PMA_REG_CTRL, 0x800);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This works with E3 only, no need to check the chip
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * before determining the port.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Drive pin low to put GPHY in reset. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_54618se_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Get speed operation status */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "54618SE read_status: 0x%x\n", legacy_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read status to clear the PHY interrupt. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_up = ((legacy_status & (1<<2)) == (1<<2));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Omitting 100Base-T4 for now */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else /* Should not happen */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Link is up in %dMbps, is_duplex_full= %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check legacy speed AN resolution */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "BCM54618SE: link speed is %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Report LP advertised speeds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_54618se_config_loopback(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "2PMA/PMD ext_phy_loopback: 54618se\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable master/slave manual mmode and set to master */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mii write 9 [bits set 11 12] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* forced 1G and disable autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set val [mii read 0] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set val [expr $val & [bits clear 6 12 13]] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set val [expr $val | [bits set 6 8]] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mii write 0 $val */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set external loopback and Tx using 6dB coding */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mii write 0x18 7 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set val [mii read 0x18] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* mii write 0x18 [expr $val | [bits set 10 15]] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl22_write(cb, phy, 0x18, val | (1<<10) | (1<<15));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This register opens the gate for the UMAC despite its name */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * length used by the MAC receive logic to check frames.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* SFX7101 PHY SECTION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_7101_config_loopback(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* SFX7101_XGXS_TEST1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_7101_config_init(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting the SFX7101 LASI indication\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore normal power mode*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* HW reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_wait_reset_complete(cb, phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Setting the SFX7101 LED to blink on traffic\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_set_pause(params, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart autoneg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Save spirom version */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_spirom_version(cb, params->port,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_7101_read_status(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "10G-base-T LASI status 0x%x->0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "10G-base-T PMA status 0x%x->0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If link is up print the AN outcome of the SFX7101 PHY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "SFX7101 AN status 0x%x->Master=%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_10G_an_resolve(cb, phy, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_ext_phy_resolve_fc(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read LP advertised speeds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Writes a self-clearing reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for clear */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_7101_hw_reset(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Low power mode is controlled by GPIO 2 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_2,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The PHY reset is controlled by GPIO 1 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_7101_set_link_led(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_SFX7101 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* STATIC PHY DECLARATION */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver = */(format_fw_ver_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic const struct elink_phy phy_serdes = {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_xgxs_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_link_settings_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_int_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver = */(format_fw_ver_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_SERDES */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_xgxs_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_link_settings_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_int_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)elink_set_xgxs_loopback,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_xgxs_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic const struct elink_phy phy_warpcore = {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.media_type = */ELINK_ETH_PHY_UNSPECIFIED,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_warpcore_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_warpcore_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_warpcore_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)elink_set_warpcore_loopback,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_warpcore_hw_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_7101_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_7101_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_common_ext_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)elink_7101_config_loopback,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_7101_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_7101_hw_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_7101_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_SFX7101 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8073_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_8073_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_8073_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_8073_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8705_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_8705_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_common_ext_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_null_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8705 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.media_type = */ELINK_ETH_PHY_SFPP_10G_FIBER,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8706_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_8706_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_common_ext_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */(ELINK_FLAGS_INIT_XGXS_FIRST |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8726_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_8726_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_8726_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)elink_8726_config_loopback,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8727_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_8727_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_8727_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_8727_hw_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_8727_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_8727_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_8481_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_848xx_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_8481_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_8481_hw_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)NULL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_848x3_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_848xx_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_848x3_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8481 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_100baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_848x3_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_848xx_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_848x3_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_84833_hw_reset_phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_100baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_848x3_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_848xx_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_848x3_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)NULL,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.format_fw_ver= */(format_fw_ver_t)elink_848xx_format_ver,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.hw_reset = */(hw_reset_t)elink_84833_hw_reset_phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_848xx_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_848xx_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_BCM84833
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic const struct elink_phy phy_54618se = {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.def_md_devad = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff},
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.mdio_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.supported = */(ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.ver_addr = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_flow_ctrl = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.req_line_speed = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.speed_cap_mask = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* req_duplex = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* rsrv = */0,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_init = */(config_init_t)elink_54618se_config_init,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.read_status = */(read_status_t)elink_54618se_read_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.link_reset = */(link_reset_t)elink_54618se_link_reset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.config_loopback = */(config_loopback_t)elink_54618se_config_loopback,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.set_link_led = */(set_link_led_t)elink_5461x_set_link_led,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /*.phy_specific_func = */(phy_specific_func_t)elink_54618se_specific_func
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/*****************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Populate the phy according. Main function: elink_populate_phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/*****************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_populate_preemphasis(struct elink_dev *cb, u32 shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Get the 4 lanes xgxs config rx and tx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (i = 0; i < 2; i++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the shmem. When num_phys is greater than 1, than this value
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * applies only to ELINK_EXT_PHY1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u32 elink_get_ext_phy_config(struct elink_dev *cb, u32 shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].external_phy_config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].external_phy_config2));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid phy_index %d\n", phy_index);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_populate_int_phy(struct elink_dev *cb, u32 shmem_base, u8 port,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_feature_config[port].link_config)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, ":chip_id = 0x%x\n", chip_id);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check Dual mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the appropriate supported and flags indications per
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * interface type of the chip
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Unknown WC interface type 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * was not set as expected. For B0, ECO will be enabled so there
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * won't be an issue there
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_SERDES */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Invalid switch_cfg\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_populate_preemphasis(cb, shmem_base, phy, port, ELINK_INT_PHY);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_populate_ext_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ext_phy_config = elink_get_ext_phy_config(cb, shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Select the phy type */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* BCM8727_NOC => BCM8727 no over current */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case external PHY wasn't found */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_populate_preemphasis(cb, shmem_base, phy, port, phy_index);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The shmem address of the phy version is located on different
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * structures. In case this structure is too old, do not set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the address
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi config2 = REG_RD(cb, shmem_base + OFFSETOF(struct shmem_region,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->ver_addr = shmem_base + OFFSETOF(struct shmem_region,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check specific mdc mdio settings */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem2_region, ext_phy_fw_version2)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check specific mdc mdio settings */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->mdio_ctrl = elink_get_emac_base(cb, mdc_mdio_access, port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Remove 100Mb link supported for BCM84833/4 when phy fw
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * version lower than or equal to 1.39
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "phy_type 0x%x port %d found in index %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, " addr=0x%x, mdio_ctl=0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_populate_phy(struct elink_dev *cb, u8 phy_index, u32 shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 shmem2_base, u8 port, struct elink_phy *phy)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_populate_int_phy(cb, shmem_base, port, phy);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi status = elink_populate_ext_phy(cb, phy_index, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_phy_def_cfg(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Populate the default phy configuration for MF mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_config = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_feature_config[params->port].link_config2));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->speed_cap_mask = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].speed_capability_mask2));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi link_config = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_feature_config[params->port].link_config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->speed_cap_mask = REG_RD(cb, params->shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi port_hw_config[params->port].speed_capability_mask));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy_index, link_config, phy->speed_cap_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu32 elink_phy_selection(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy_config_swapped = params->multi_phy_config &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_probe(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 phy_config_swapped, sync_offset, media_types;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy_config_swapped = params->multi_phy_config &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "phy_config_swapped %x, phy_index %x,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " actual_phy_idx %x\n", phy_config_swapped,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, params->shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "phy probe failed in phy index %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[params->port].media_type);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update media type for non-PMF sync only for the first time
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * In case the media type changes afterwards, it will be updated
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * using the update_status function
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "End phy probe. #phys found %x\n", params->num_phys);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu8 elink_phy_is_temperature_support(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* This function check that at least one of the phy's supports
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * temperature read.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed = params->req_line_speed[0];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case link speed is auto, set speed the highest as possible */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->line_speed < ELINK_SPEED_10000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line speed %d while UMAC is"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " disabled!\n", params->req_line_speed[0]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line speed %d for UMAC\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Link speed >= 10000 requires XMAC enabled */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line speed %d while XMAC is"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi " disabled!\n", params->req_line_speed[0]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check link speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid line speed %d for XMAC\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_init_emul(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_init_e3_emul_mac(params, vars) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* update shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_EMUL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_init_fpga(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable on E1.5 FPGA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed = params->req_line_speed[0];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Invalid link speed %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifdef ELINK_INCLUDE_FPGA
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_init_bmac_loopback(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set bmac loopback */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_init_emac_loopback(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set bmac loopback */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_init_xmac_loopback(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->line_speed = params->req_line_speed[0];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set WC to loopback mode since link is required to provide clock
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to the XMAC in 20G mode
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_aer_mmd(params, ¶ms->phy[0]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_reset_lane(cb, ¶ms->phy[0], 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->phy[ELINK_INT_PHY].config_loopback(
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_init_umac_loopback(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_init_xgxs_loopback(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->req_line_speed[0] == ELINK_SPEED_1000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->req_line_speed[0] == ELINK_SPEED_1000) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set 10G XGXS loopback */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set external phy loopback */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[phy_index].config_loopback)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifdef ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_set_rx_filter(struct elink_params *params, u8 en)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Open / close the gate between the NIG and the BRB */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifdef ELINK_ENHANCEMENTS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_avoid_link_flap(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Sync the link parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * The module verification was already done by previous link owner,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * so this call is meant only to get warning message
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[phy_idx];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Calling PHY specific func\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Re-enable the NIG/MAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bmac_enable(params, vars, 0, !dont_clear_stat);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Increment LFA count */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear link flap reason */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable NIG DRAIN */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable interrupts */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_cannot_avoid_link_flap(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Store the new link parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->req_duplex[0] | (params->req_duplex[1] << 16));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, req_line_speed),
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->req_line_speed[0] | (params->req_line_speed[1] << 16));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, additional_config));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, additional_config), tmp_val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear the "Don't Clear Statistics" bit, and set reason */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set link flap reason */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Increment link flap counter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Proceed with regular link initialization */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Phy Initialization started\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "(1) req_speed %d, req_flowctrl %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->req_line_speed[0], params->req_flow_ctrl[0]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "(2) req_speed %d, req_flowctrl %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->req_line_speed[1], params->req_flow_ctrl[1]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_flags = ELINK_PHY_INITIALIZED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Driver opens NIG-BRB filters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check if link flap can be avoided */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Link Flap Avoidance in progress\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_avoid_link_flap(params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Cannot avoid link flap lfa_sta=0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cannot_avoid_link_flap(params, vars, lfa_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable attentions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //ELINK_INCLUDE_EMUL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_PFC_ENABLED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "No phy found for initialization !!\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Num of phys on board: %d\n", params->num_phys);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_FPGA */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_EMUL */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_INCLUDE_LOOPBACK */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_SERDES
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_XGXS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_LOOPBACK
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng_eee(params, vars->eee_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM84833 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 phy_index, port = params->port, clear_latch_ind = 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Resetting the link of port %d\n", port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable attentions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng_eee(params, vars->eee_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM84833 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Activate nig drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable nig egress interface */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Stop BigMac rx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_EMUL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_bmac_rx(cb, params->chip_id, port, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Stop XMAC/UMAC rx */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_INCLUDE_EMUL
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable emac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The PHY reset is controlled by GPIO 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Hold it as vars low
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear link led */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear latching indication */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_LATCH_BC_0 + port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable nig ingress interface */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset BigMac */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_LINK_RESET
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_lfa_reset(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi params->link_flags &= ~ELINK_PHY_INITIALIZED;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Activate NIG drain so that during this time the device won't send
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * anything while it is unable to response.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Close gracefully the gate from BMAC to NIG such that no half packets
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * are passed.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_bmac_rx(cb, params->chip_id, params->port, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait 10ms for the pipe to clean up*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clean the NIG-BRB using the network filters in a way that will
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * not cut a packet in the middle.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Re-open the gate between the BMAC and the NIG, after verifying the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * gate to the BRB is closed, otherwise packets may arrive to the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * firmware before driver had initialized it. The target is to achieve
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * minimum management protocol down time.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_bmac_rx(cb, params->chip_id, params->port, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable NIG drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/****************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Common function */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/****************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8073_common_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PART1 - Reset both phys */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (port = PORT_MAX - 1; port >= PORT_0; port--) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In E2, same phy is using for port0 of the two paths */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Extract the ext phy address for the port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate_phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable attentions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Need to take the phy out of low power mode in order
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to write to access its registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Add delay of 150ms after reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PART2 - Download firmware to both phys */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (port = PORT_MAX - 1; port >= PORT_0; port--) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_8073_8727_external_rom_boot(cb, phy_blk[port],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Only set bit 10 = 1 (Tx power down) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Phase1 of TX_POWER_DOWN reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Toggle Transmitter: Power down and then up with 600ms delay
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (port = PORT_MAX - 1; port >= PORT_0; port--) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Phase2 of POWER_DOWN_RESET */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Release bit 10 (Release Tx power down) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read modify write the SPI-ROM version select register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* set GPIO2 back to LOW */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8726_common_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Use port1 because of the static port-swap */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable the module detection interrupt */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In E2, same phy is using for port0 of the two paths */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Extract the ext phy address for the port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset phy*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set fault module detected LED on */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_get_ext_phy_reset_gpio(struct elink_dev *cb, u32 shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 phy_gpio_reset = REG_RD(cb, shmem_base +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[PORT_0].default_cfg));
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Don't override the io_gpio and io_port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_8727_common_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Retrieve the reset gpio/port which control the reset.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Default is GPIO1, PORT1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_get_ext_phy_reset_gpio(cb, shmem_base_path[0],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Calculate the port based on port swap */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initiate PHY reset*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PART1 - Reset both phys */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (port = PORT_MAX - 1; port >= PORT_0; port--) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In E2, same phy is using for port0 of the two paths */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Extract the ext phy address for the port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* disable attentions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Add delay of 150ms after reset */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PART2 - Download firmware to both phys */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (port = PORT_MAX - 1; port >= PORT_0; port--) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_8073_8727_external_rom_boot(cb, phy_blk[port],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable PHY transmitter output */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM8727_BCM8073 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_84833_common_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, chip_id);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "84833 reset pulse on pin values 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_84833_pre_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Wait for FW completing its initialization. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "84833 reset timeout\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Put the port in super isolate mode. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Save spirom version */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_save_848xx_spirom_version(phy, cb, port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_pre_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, ELINK_EXT_PHY1, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate_phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_clk(cb, chip_id, phy.mdio_ctrl);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_84833_pre_init_phy(cb, &phy, port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_FROM_BNX2X */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM84833 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_ext_phy_common_init(struct elink_dev *cb, u32 shmem_base_path[],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_8073_common_init_phy(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_8727_common_init_phy(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* GPIO1 affects both ports, so there's need to pull
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * it for single port alone
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_8726_common_init_phy(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* GPIO3's are linked, and so both need to be toggled
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to obtain required 2us pulse.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc = elink_84833_common_init_phy(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi "ext_phy 0x%x common init not required\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Port %d\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic elink_status_t elink_warpcore_common_init(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Procedure to bring the LCPLL out of reset. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Resetting Warpcore\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_reset_warpcore(cb) != ELINK_STATUS_OK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Extract the ext phy address for the port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base_path[0],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set WC to use CL45 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set swap lanes and polarity */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi wc_lane_config = REG_RD(cb, shmem_base_path[0] +
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Power down warpcore lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_powerdown_secondport_lanes(cb, &phy);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable sequencer */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_lane_swap(cb, &phy, wc_lane_config);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_lane_polarity(cb, &phy, wc_lane_config);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_set_dual_mode(cb, &phy, shmem_base_path[0]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Load Warpcore microcode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* RX traffic and TX traffic requires clock sync.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * When transmiting we send data + clock to the Warpcore.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * This clock is provided by lane 0 of the Warpcore.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * So we need to configure this lane to supply us the correct clock
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * which will be use for transmit on all lanes
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* To force tx_wclk33 to txckp[0] */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy.supported & ELINK_SUPPORTED_20000baseKR2_Full)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Dual mode - lanes 0,1 use same clocks/resets - from lane 0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Lanes 2,3 use same clocks/resets - from lane 2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable sequencer */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* INCLUDE_WARPCORE_UC_LOAD */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (CHIP_REV_IS_EMUL(chip_id) || CHIP_REV_IS_FPGA(chip_id))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Begin common phy init\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable EPIO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check if common init was already done */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Not doing common init; phy ver is 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc |= elink_warpcore_common_init(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read the ext_phy_type for arbitrary port(0) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ext_phy_config = elink_get_ext_phy_config(cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi rc |= elink_ext_phy_common_init(cb, shmem_base_path,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_EMUL_ONLY */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // #ifndef EXCLUDE_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_check_over_curr(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Ignore check if no external input PIN available */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_get_cfg_pin(cb, cfg_pin, &pin_val) != ELINK_STATUS_OK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " been detected and the power to "
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // "that SFP+ module has been removed"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " to prevent failure of the card."
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " Please remove the SFP+ module and"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " restart the system to clear this"
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // " error.\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_WARPCORE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Returns 0 if no change occured since last check; 1 otherwise. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic u8 elink_analyze_link_error(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Compare new value with previous value */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If values differ */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Analyze Remote Fault\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "Link changed:[%x %x]->%x\n", vars->link_up,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Do not touch the link in case physical link down */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* a. Update shmem->link_status accordingly
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * b. Update elink_vars->link_up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* activate nig drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set LED mode to off since the PHY doesn't know about these
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear nig drain */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_57711E_SUPPORT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update the LED according to the link state */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update link status in the shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* C. Trigger General Attention */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EDEBUG
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/******************************************************************************
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* Description:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* This function checks for half opened connection change indication.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* When such change occurs, it calls the elink_analyze_link_error
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* to check if Remote Fault is set or cleared. Reception of remote fault
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* status message in the MAC indicates that the peer's MAC has detected
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi* a fault, for example, due to break in the TX side of fiber.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi******************************************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_check_half_open_conn(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case link status is physically up @ 10G do */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (REG_RD(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check E3 XMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Note that link speed cannot be queried here, since it may be
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * zero while link is down. In case UMAC is active, LSS will
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * simply not be set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clear stick bits (Requires rising edge) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (REG_RD(cb, mac_base + XMAC_REG_RX_LSS_STATUS))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_analyze_link_error(params, vars, lss_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi } else if (REG_RD(cb, MISC_REG_RESET_REG_2) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Check E1X / E2 BMAC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_RD_DMAE(cb, mac_base + lss_status_reg, wb_data, 2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_analyze_link_error(params, vars, lss_status,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_sfp_tx_fault_detection(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cfg_pin = (REG_RD(cb, params->shmem_base + OFFSETOF(struct shmem_region,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_get_cfg_pin(cb, cfg_pin, &value)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Failed to read pin 0x%02x\n", cfg_pin);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi led_change = elink_analyze_link_error(params, vars, value,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Change TX_Fault led, set link status for further syncs */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* If module is unapproved, led should be on regardless */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P1(cb, "Change TX_Fault LED: ->%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_e3_module_fault_led(params, led_mode);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_kr2_recovery(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_DEBUG
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_enable_AN_KR2(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchistatic void elink_check_kr2_wa(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 base_page, next_page, not_kr2_device, lane;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Since some switches tend to reinit the AN process and clear the
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * and recovered many times
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi sigdet = elink_warpcore_get_sigdet(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* CL73 has not begun yet */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case NP bit is not set in the BasePage, or it is set,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * but only KX is advertised, declare this link partner as non-KR2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi not_kr2_device = (((base_page & 0x8000) == 0) ||
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* In case KR2 is already disabled, check if we need to re-enable it */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* KR2 is enabled, but not KR2 device */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Disable KR2 on both lanes */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, next_page);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restart AN on leading lane */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_period_func(struct elink_params *params, struct elink_vars *vars)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#if defined(ELINK_DEBUG) || defined(ELINK_ENHANCEMENTS)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_check_half_open_conn(params, vars, 1) !=
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "Fault detection failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if ((phy->flags & ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC) == 0) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_is_sfp_module_plugged(phy, params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (!elink_is_sfp_module_plugged(phy, params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_warpcore_config_runtime(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_is_sfp_module_plugged(phy, params)) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_sfp_tx_fault_detection(phy, params, vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Clean trail, interrupt corrects the leds */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Update link status in the shared memory */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_update_mng(params, vars->link_status);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu8 elink_fan_failure_det_req(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_enable_pmd_tx(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_set_mdio_emac_per_phy(params->cb, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_cl45_write(params->cb, ¶ms->phy[phy_index],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_AUX_POWER
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_hw_reset_phy(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 chip_id, u32 shmem_base, u32 shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (elink_populate_phy(cb, phy_index, shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P0(cb, "populate phy failed\n");
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set GPIO3 to trigger SFP+ module insertion/removal */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_SET_GPIO(cb, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi dev_info.port_hw_config[port].aeu_int_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi REG_WR(cb, sync_offset, vars->aeu_int_mask);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEBUG_P3(cb, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Open appropriate AEU for interrupts */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Enable the GPIO to trigger interrupt */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // ELINK_ENHANCEMENTS
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // EXCLUDE_NON_COMMON_INIT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_adjust_phy_func_ptr(struct elink_params *params)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Select the phy type */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_BCM87x6 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_phy->config_loopback = phy.config_loopback;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_phy->format_fw_ver = phy.format_fw_ver;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi cur_phy->phy_specific_func = phy.phy_specific_func;
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_get_phy_temperature(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The temperature returned from this function is expected
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * to be degree C. Any conversion from hardware value to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * degree C will be performed here.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi for (idx = 0; idx < params->num_phys; idx++) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi if (phy->flags & ELINK_FLAGS_TEMPERATURE) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiint get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi return elink_get_cfg_pin(cb, pin_cfg, val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_force_link(struct elink_params *params, int enable) {
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 lane = elink_get_warpcore_lane(phy, params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Global register - operate on lane 0 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Restore AER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_WARPCORE */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* #ifndef EXCLUDE_COMMON_INIT */