Searched defs:reg_val (Results 1 - 25 of 25) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/sys/i2c/clients/
H A Di2c_gpio.h49 uint32_t reg_val; member in struct:i2c_gpio
/illumos-gate/usr/src/uts/common/io/
H A Dpci_cap.c201 * 16-bits of the cap header matches <reg_val> after masking the value
202 * with <reg_mask>; if both <reg_mask> and <reg_val> are 0, it will return
206 pci_htcap_locate(ddi_acc_handle_t h, uint16_t reg_mask, uint16_t reg_val, argument
235 reg_mask) == reg_val) {
/illumos-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c430 uint32_t reg_val, hw_index; local
437 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
438 ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val);
439 reg_val = IXGBE_READ_REG(hw, IXGBE_STATUS);
440 ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val);
441 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
442 ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val);
443 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
444 ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val);
449 reg_val
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H A Dixgbe_gld.c102 uint32_t reg_val; local
111 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
114 reg_val |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
116 reg_val &= (~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE));
118 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_FCTRL, reg_val);
H A Dixgbe_main.c2311 uint32_t reg_val; local
2355 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index));
2356 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */
2360 reg_val |= 0x0020; /* pthresh */
2362 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val);
2368 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2369 reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS);
2370 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2377 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) |
2379 reg_val |
2388 uint32_t reg_val; local
2568 uint32_t reg_val; local
2657 uint32_t reg_val; local
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_init.h200 u32 reg_val; local
203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr);
206 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
208 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val);
252 u32 reg_val, mcp_aeu_bits = local
268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i].
270 if (reg_val & reg_mask) {
274 reg_val & reg_mask);
280 reg_val
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/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c362 uint32_t reg_val = 0; local
365 reg_val = val & 0xffffffff;
367 return (reg_val);
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hio_guest.c180 int *reg_val; local
206 0, "reg", &reg_val, &reg_len) != DDI_PROP_SUCCESS) {
211 cookie = (uint32_t)(reg_val[0]);
212 ddi_prop_free(reg_val);
/illumos-gate/usr/src/uts/sun4u/io/i2c/clients/
H A Dadm1026.c65 * in the ioctl call. The reg_mask and reg_val members of i2c_gpio_t are
68 * that the user wants to read or modify and reg_val has the actual value of
440 adm1026_send8(adm1026_unit_t *unitp, uint8_t reg, uint8_t reg_val, argument
449 val |= (reg_val & reg_mask);
484 uint8_t reg_val = 0; local
488 err = adm1026_get8(unitp, ADM1026_STS_REG5, &reg_val);
492 *val = reg_val;
496 err = adm1026_get8(unitp, ADM1026_STS_REG6, &reg_val);
500 *val |= ((reg_val << OUTPUT_SHIFT) & (mask & 0xff00));
636 err = adm1026_set_output(unitp, g_buf.reg_val, g_bu
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/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_i210.c829 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; local
836 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
837 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);
865 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
866 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
874 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
875 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
H A De1000_82575.c2277 u32 reg_val, reg_offset; local
2291 reg_val = E1000_READ_REG(hw, reg_offset);
2293 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2298 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2300 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2303 E1000_WRITE_REG(hw, reg_offset, reg_val);
/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000g_rx.c152 uint32_t reg_val; local
359 reg_val =
363 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val);
370 reg_val = E1000_READ_REG(hw, E1000_RFCTL);
371 reg_val |= (E1000_RFCTL_IPV6_EX_DIS |
373 E1000_WRITE_REG(hw, E1000_RFCTL, reg_val);
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dglue.c90 t1_read_reg_4(ch_t *obj, uint32_t reg_val) argument
92 return (ddi_get32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0 + reg_val)));
96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) argument
98 ddi_put32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0+reg_val), write_val);
/illumos-gate/usr/src/uts/common/io/igb/
H A Digb_gld.c479 uint32_t reg_val; local
488 reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL);
491 reg_val |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
493 reg_val &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE));
495 E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val);
H A Digb_main.c2290 uint32_t reg_val; local
2343 reg_val = E1000_READ_REG(hw,
2345 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2347 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2365 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2366 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2367 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2380 uint32_t reg_val; local
2391 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2392 reg_val
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/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_vf.c249 u32 reg_val; local
270 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));
271 reg_val &= ~IXGBE_RXDCTL_ENABLE;
272 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
H A Dixgbe_82599.c244 * @reg_val: Value we read from AUTOC
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) argument
265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
272 * @reg_val: value to write to AUTOC
H A Dixgbe_x550.c1415 u32 reg_val; local
1419 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1423 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1424 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1429 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1433 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1436 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1439 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1713 u16 reg_slice, reg_val; local
1734 reg_val
1791 u32 reg_val; local
1995 u32 reg_val; local
2834 u32 pause, asm_dir, reg_val; local
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H A Dixgbe_common.c1061 u32 reg_val; local
1087 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1088 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1089 reg_val |= IXGBE_RXDCTL_SWFLSH;
1090 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
3290 * @reg_val: Value we read from AUTOC
3294 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) argument
3297 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3304 * @reg_val: value to write to AUTOC
3310 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, boo argument
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/illumos-gate/usr/src/lib/libprtdiag_psr/sparc/opl/common/
H A Dopl_picl.c104 int *reg_val; local
196 reg_val = malloc(pinfo.size);
197 if (reg_val == NULL)
202 (nodeh, OBP_PROP_REG, reg_val, pinfo.size);
205 free(reg_val);
210 if (reg_val[0] != 0) {
212 (((reg_val[0]) & PCI_DEV_MASK) >> 11);
214 (((reg_val[0]) & PCI_FUNC_MASK) >> 8);
216 (((reg_val[0]) & PCI_BUS_MASK) >> 16);
218 free(reg_val);
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/illumos-gate/usr/src/uts/common/io/1394/targets/dcam1394/
H A Ddcam_param.c56 uint_t reg_val);
1705 feature_csr_val_subparam_extract(uint_t subparam, uint_t reg_val) argument
1712 ret_val = (reg_val & DCAM1394_MASK_PRESENCE_INQ) >>
1717 ret_val = (reg_val & DCAM1394_MASK_ON_OFF) >>
1722 ret_val = (reg_val & DCAM1394_MASK_A_M_MODE) >>
1727 ret_val = (reg_val & DCAM1394_MASK_VALUE) >>
1732 ret_val = (reg_val & DCAM1394_MASK_U_VALUE) >>
1738 ret_val = (reg_val & DCAM1394_MASK_V_VALUE) >>
1760 uint_t reg_val)
1767 ret_val = (reg_val
1759 feature_elm_inq_reg_val_subparam_extract(uint_t subparam, uint_t reg_val) argument
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_access.c412 u32_t reg_val = 0; local
491 reg_val = REG_RD(pdev, MISC_REG_GPIO);
492 DbgMessage(NULL, INFORM, "lm_gpio_read: MISC_REG_GPIO value 0x%x mask 0x%x\n", reg_val, mask);
495 if ((reg_val & mask) == mask)
734 u32_t reg_val = 0, mask = 0; local
737 reg_val = REG_RD(pdev, MISC_REG_SPIO);
739 DbgMessage(pdev, INFORM, "lm_spio_read: MISC_REG_SPIO value is 0x%x\n", reg_val);
756 reg_val |= (MISC_SPIO_SPIO4 << MISC_SPIO_FLOAT_POS);
760 reg_val |= (MISC_SPIO_SPIO5 << MISC_SPIO_FLOAT_POS);
764 reg_val |
807 u32_t reg_val = 0; local
924 u32_t reg_val = 0; local
1023 u32_t reg_val = 0; local
1094 u32_t reg_val = 0; local
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/illumos-gate/usr/src/uts/common/io/nge/
H A Dnge_chip.c676 uint32_t reg_val; local
698 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK);
699 reg_val &= ~NGE_INTR_ALL_EN;
700 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val);
/illumos-gate/usr/src/uts/common/io/i40e/core/
H A Di40e_common.c1153 u32 reg_val; local
1160 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1161 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1162 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1165 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1169 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
2949 * @reg_val: register value
2955 u32 reg_addr, u64 *reg_val,
2963 if (reg_val
2954 i40e_aq_debug_read_register(struct i40e_hw *hw, u32 reg_addr, u64 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
2989 i40e_aq_debug_write_register(struct i40e_hw *hw, u32 reg_addr, u64 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c5673 u16 reg_val; local
5678 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5682 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5684 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5689 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5695 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5696 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5698 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5700 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5702 reg_val
5776 u16 reg_val; local
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