/******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD$*/
#include "ixgbe_type.h"
#include "ixgbe_82599.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
bool autoneg_wait_to_complete);
{
DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
/*
* enable the laser control functions for SFP+ fiber
* and MNG not enabled
*/
!ixgbe_mng_enabled(hw)) {
} else {
}
/* Set up dual speed SFP+ support */
} else {
} else {
}
}
}
/**
* @hw: pointer to hardware structure
*
* Initialize any function pointers that were not able to be
* not known. Perform the SFP init if necessary.
*
**/
{
DEBUGFUNC("ixgbe_init_phy_ops_82599");
/* Store flag indicating I2C bus access control unit. */
/* Initialize access to QSFP+ I2C bus */
esdp &= ~IXGBE_ESDP_SDP1_DIR;
esdp &= ~IXGBE_ESDP_SDP0;
}
/* Identify the PHY or SFP module */
if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto init_phy_ops_out;
/* Setup function pointers based on detected SFP module and speeds */
/* If copper media, overwrite with copper function pointers */
}
/* Set necessary function pointers based on PHY type */
case ixgbe_phy_tn:
break;
default:
break;
}
return ret_val;
}
{
DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
&data_offset);
if (ret_val != IXGBE_SUCCESS)
goto setup_sfp_out;
/* PHY config will finish before releasing the semaphore */
if (ret_val != IXGBE_SUCCESS) {
goto setup_sfp_out;
}
goto setup_sfp_err;
while (data_value != 0xffff) {
goto setup_sfp_err;
}
/* Release the semaphore */
/* Delay obtaining semaphore again to allow FW access
* prot_autoc_write uses the semaphore too.
*/
/* Restart DSP and set SFI mode */
FALSE);
if (ret_val) {
DEBUGOUT("sfp module setup not complete\n");
goto setup_sfp_out;
}
}
return ret_val;
/* Release the semaphore */
/* Delay obtaining semaphore again to allow FW access */
"eeprom read at offset %d failed", data_offset);
return IXGBE_ERR_PHY;
}
/**
* prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
* @hw: pointer to hardware structure
* @locked: Return the if we locked for this read.
* @reg_val: Value we read from AUTOC
*
* For this part (82599) we need to wrap read-modify-writes with a possible
* prot_autoc_write_82599().
*/
{
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
if (ret_val != IXGBE_SUCCESS)
return IXGBE_ERR_SWFW_SYNC;
}
return IXGBE_SUCCESS;
}
/**
* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure
* @reg_val: value to write to AUTOC
* previous proc_autoc_read_82599.
*
* AUTOC. Likewise after a write we need to do a pipeline reset.
*/
{
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
goto out;
/* We only need to get the lock if:
* - We didn't do it already (in the read part of a read-modify-write)
* - LESM is enabled.
*/
if (ret_val != IXGBE_SUCCESS)
return IXGBE_ERR_SWFW_SYNC;
}
out:
* already had it when this function was called.
*/
if (locked)
return ret_val;
}
/**
* ixgbe_init_ops_82599 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and assign the MAC type for 82599.
* Does not touch the hardware.
**/
{
DEBUGFUNC("ixgbe_init_ops_82599");
/* PHY */
/* MAC */
/* RAR, Multicast, VLAN */
/* Link */
/* EEPROM */
/* Manageability interface */
return ret_val;
}
/**
* ixgbe_get_link_capabilities_82599 - Determines link capabilities
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @autoneg: TRUE when autoneg or autotry is enabled
*
* Determines the link capabilities by reading the AUTOC register.
**/
bool *autoneg)
{
DEBUGFUNC("ixgbe_get_link_capabilities_82599");
/* Check if 1G SFP module. */
goto out;
}
/*
* Determine link capabilities based on the stored value of AUTOC,
* which represents EEPROM defaults. If AUTOC value has not
* been stored, use the current register values.
*/
else
switch (autoc & IXGBE_AUTOC_LMS_MASK) {
break;
break;
case IXGBE_AUTOC_LMS_1G_AN:
break;
break;
if (autoc & IXGBE_AUTOC_KR_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KX_SUPP)
break;
if (autoc & IXGBE_AUTOC_KR_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KX_SUPP)
break;
break;
default:
goto out;
break;
}
/* QSFP must not enable full auto-negotiation
* Limited autoneg is enabled at 1G
*/
else
}
out:
return status;
}
/**
* ixgbe_get_media_type_82599 - Get media type
* @hw: pointer to hardware structure
*
* Returns the media type (fiber, copper, backplane)
**/
{
DEBUGFUNC("ixgbe_get_media_type_82599");
/* Detect if there is a copper PHY attached. */
case ixgbe_phy_cu_unknown:
case ixgbe_phy_tn:
goto out;
default:
break;
}
case IXGBE_DEV_ID_82599_KX4:
case IXGBE_DEV_ID_82599_KR:
break;
case IXGBE_DEV_ID_82599_SFP:
case IXGBE_DEV_ID_82599EN_SFP:
break;
case IXGBE_DEV_ID_82599_CX4:
break;
break;
break;
break;
default:
break;
}
out:
return media_type;
}
/**
* ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
* @hw: pointer to hardware structure
*
* Disables link during D3 power down sequence.
*
**/
{
DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
}
}
/**
* ixgbe_start_mac_link_82599 - Setup MAC link settings
* @hw: pointer to hardware structure
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed.
**/
bool autoneg_wait_to_complete)
{
u32 i;
DEBUGFUNC("ixgbe_start_mac_link_82599");
/* reset_pipeline requires us to hold this lock as it writes to
* AUTOC.
*/
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
if (status != IXGBE_SUCCESS)
goto out;
}
/* Restart link */
if (got_lock)
/* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) {
if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
(autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
(autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
links_reg = 0; /* Just in case Autoneg time = 0 */
for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
if (links_reg & IXGBE_LINKS_KX_AN_COMP)
break;
msec_delay(100);
}
if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
DEBUGOUT("Autoneg did not complete.\n");
}
}
}
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
out:
return status;
}
/**
* ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
* @hw: pointer to hardware structure
*
* The base drivers may require better control over SFP+ module
* PHY states. This includes selectively shutting down the Tx
* laser on the PHY, effectively halting physical link.
**/
{
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
return;
/* Disable Tx laser; allow 100us to go dark per spec */
usec_delay(100);
}
/**
* ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
* @hw: pointer to hardware structure
*
* The base drivers may require better control over SFP+ module
* PHY states. This includes selectively turning on the Tx
* laser on the PHY, effectively starting physical link.
**/
{
/* Enable Tx laser; allow 100ms to light up */
esdp_reg &= ~IXGBE_ESDP_SDP3;
msec_delay(100);
}
/**
* ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
* @hw: pointer to hardware structure
*
* When the driver changes the link speeds that it can support,
* it sets autotry_restart to TRUE to indicate that we need to
* initiate a new autotry session with the link partner. To do
* so, we set the speed then disable and re-enable the Tx laser, to
* alert the link partner that it also needs to restart autotry on its
* end. This is consistent with TRUE clause 37 autoneg, which also
* involves a loss of signal.
**/
{
DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
return;
}
}
/**
* ixgbe_set_hard_rate_select_speed - Set module link speed
* @hw: pointer to hardware structure
* @speed: link speed to set
*
*/
{
switch (speed) {
break;
esdp_reg &= ~IXGBE_ESDP_SDP5;
break;
default:
DEBUGOUT("Invalid fixed module speed\n");
return;
}
}
/**
* ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Implements the Intel SmartSpeed algorithm.
**/
bool autoneg_wait_to_complete)
{
s32 i, j;
DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
/* Set autoneg_advertised value based on input link speed */
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
if (speed & IXGBE_LINK_SPEED_100_FULL)
/*
* Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
* autoneg advertisement if link is unable to be established at the
* highest negotiated rate. This can sometimes happen due to integrity
* issues with the physical media connection.
*/
/* First, try to get link with full advertisement */
for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
if (status != IXGBE_SUCCESS)
goto out;
/*
* Wait for the controller to acquire link. Per IEEE 802.3ap,
* Section 73.10.2, we may have to wait up to 500ms if KR is
* Table 9 in the AN MAS.
*/
for (i = 0; i < 5; i++) {
msec_delay(100);
/* If we have link, just jump out */
FALSE);
if (status != IXGBE_SUCCESS)
goto out;
if (link_up)
goto out;
}
}
/*
*/
if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
goto out;
/* Turn SmartSpeed on to disable KR support */
if (status != IXGBE_SUCCESS)
goto out;
/*
* Wait for the controller to acquire link. 600ms will allow for
* the AN link_fail_inhibit_timer as well for multiple cycles of
* parallel detect, both 10g and 1g. This allows for the maximum
* connect attempts as defined in the AN MAS table 73-7.
*/
for (i = 0; i < 6; i++) {
msec_delay(100);
/* If we have link, just jump out */
if (status != IXGBE_SUCCESS)
goto out;
if (link_up)
goto out;
}
/* We didn't get link. Turn SmartSpeed back off. */
out:
DEBUGOUT("Smartspeed has downgraded the link speed "
"from the maximum advertised\n");
return status;
}
/**
* ixgbe_setup_mac_link_82599 - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Set the link speed in the AUTOC register and restarts link.
**/
bool autoneg_wait_to_complete)
{
u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
u32 i;
DEBUGFUNC("ixgbe_setup_mac_link_82599");
/* Check to see if speed passed in is supported. */
if (status)
goto out;
if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
goto out;
}
else
orig_autoc = autoc;
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
/* Switch from 1G SFI to 10G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
}
} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
(link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
/* Switch from 10G SFI to 1G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
(pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
else
}
}
if (autoc != current_autoc) {
/* Restart link */
if (status != IXGBE_SUCCESS)
goto out;
/* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) {
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
links_reg = 0; /*Just in case Autoneg time=0*/
for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
if (links_reg & IXGBE_LINKS_KX_AN_COMP)
break;
msec_delay(100);
}
if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
status =
DEBUGOUT("Autoneg did not complete.\n");
}
}
}
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
}
out:
return status;
}
/**
* ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg_wait_to_complete: TRUE if waiting is needed to complete
*
* Restarts link on PHY and MAC based on settings passed in.
**/
bool autoneg_wait_to_complete)
{
DEBUGFUNC("ixgbe_setup_copper_link_82599");
/* Setup the PHY according to input speed */
/* Set up MAC */
return status;
}
/**
* ixgbe_reset_hw_82599 - Perform hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by resetting the transmit and receive units, masks
* and clears all interrupts, perform a PHY reset, and perform a link (MAC)
* reset.
**/
{
DEBUGFUNC("ixgbe_reset_hw_82599");
if (status != IXGBE_SUCCESS)
goto reset_hw_out;
/* flush pending Tx transactions */
/* PHY ops must be identified and initialized prior to reset */
/* Identify PHY and related function pointers */
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
/* Setup SFP module if there is one present. */
}
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
/* Reset PHY */
/* remember AUTOC from before we reset */
/*
* Issue global reset to the MAC. Needs to be SW reset if link is up.
* If link reset is used when link is up, it might reset the PHY when
* mng is using it. If link is down or the flag to force full link
* reset is set, then perform link reset.
*/
if (!hw->force_full_reset) {
if (link_up)
}
/* Poll for reset bit to self-clear meaning reset is complete */
for (i = 0; i < 10; i++) {
usec_delay(1);
if (!(ctrl & IXGBE_CTRL_RST_MASK))
break;
}
if (ctrl & IXGBE_CTRL_RST_MASK) {
DEBUGOUT("Reset polling failed to complete.\n");
}
msec_delay(50);
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to
* allow time for any pending HW events to complete.
*/
goto mac_reset_top;
}
/*
* stored off yet. Otherwise restore the stored original
* values since the reset operation sets back to defaults.
*/
/* Enable link if disabled in NVM */
if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
}
} else {
/* If MNG FW is running on a multi-speed device that
* doesn't autoneg with out driver support we need to
* leave LMS in the state it was before we MAC reset.
* Likewise if we support WoL we don't want change the
* LMS state.
*/
FALSE);
if (status != IXGBE_SUCCESS)
goto reset_hw_out;
}
if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
}
}
/* Store the permanent mac address */
/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table. Also reset num_rar_entries to 128,
* since we modify this value when programming the SAN MAC address.
*/
/* Store the permanent SAN mac address */
/* Add the SAN MAC address to the RAR only if it's a valid address */
/* Save the SAN MAC RAR index */
/* Reserve the last RAR for the SAN MAC address */
}
return status;
}
/**
* ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
* @hw: pointer to hardware structure
* @fdircmd: current value of FDIRCMD register
*/
{
int i;
for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
return IXGBE_SUCCESS;
usec_delay(10);
}
return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
}
/**
* ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
* @hw: pointer to hardware structure
**/
{
int i;
DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
/*
* Before starting reinitialization process,
* FDIRCMD.CMD must be zero.
*/
if (err) {
DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
return err;
}
/*
* 82599 adapters flow director init flow cannot be restarted,
* Workaround 82599 silicon errata by performing the following steps
* before re-writing the FDIRCTRL control register with the same value.
* - write 1 to bit 8 of FDIRCMD register &
* - write 0 to bit 8 of FDIRCMD register
*/
/*
* Clear FDIR Hash register to clear any leftover hashes
* waiting to be programmed.
*/
/* Poll init-done after we write FDIRCTRL register */
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
break;
msec_delay(1);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
DEBUGOUT("Flow Director Signature poll time exceeded!\n");
return IXGBE_ERR_FDIR_REINIT_FAILED;
}
/* Clear FDIR statistics registers (read to clear) */
return IXGBE_SUCCESS;
}
/**
* ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
* @hw: pointer to hardware structure
* @fdirctrl: value to write to flow director control register
**/
{
int i;
DEBUGFUNC("ixgbe_fdir_enable_82599");
/* Prime the keys for hashing */
/*
* Poll init-done after we write the register. Estimated times:
* 10G: PBALLOC = 11b, timing is 60us
* 1G: PBALLOC = 11b, timing is 600us
* 100M: PBALLOC = 11b, timing is 6ms
*
* Multiple these timings by 4 if under full Rx load
*
* So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
* 1 msec per poll time. If we're at line rate and drop to 100M, then
* this might not finish in our poll time, but we can live with that
* for now.
*/
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
break;
msec_delay(1);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL)
DEBUGOUT("Flow Director poll time exceeded!\n");
}
/**
* ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
* @hw: pointer to hardware structure
* @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation
**/
{
DEBUGFUNC("ixgbe_init_fdir_signature_82599");
/*
* Continue setup of fdirctrl register bits:
* Move the flexible bytes to use the ethertype - shift 6 words
* Set the maximum length per hash bucket to 0xA filters
* Send interrupt when 64 filters are left
*/
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
/* write hashes and fdirctrl register, poll for completion */
return IXGBE_SUCCESS;
}
/**
* ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
* @hw: pointer to hardware structure
* @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation
* @cloud_mode: TRUE - cloud mode, FALSE - other mode
**/
bool cloud_mode)
{
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/*
* Continue setup of fdirctrl register bits:
* Turn perfect match filtering on
* Report hash in RSS field of Rx wb descriptor
* Initialize the drop queue to queue 127
* Move the flexible bytes to use the ethertype - shift 6 words
* Set the maximum length per hash bucket to 0xA filters
* Send interrupt when 64 (0x4 * 16) filters are left
*/
(0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
if (cloud_mode)
/* write hashes and fdirctrl register, poll for completion */
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
* @hw: pointer to hardware structure
* @dropqueue: Rx queue index used for the dropped packets
**/
{
DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
/* Clear init done bit and drop queue field */
/* Set drop queue */
/* write hashes and fdirctrl register, poll for completion */
}
/*
* These defines allow us to quickly generate all of the necessary instructions
* in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
* for values 0 through 15
*/
#define IXGBE_ATR_COMMON_HASH_KEY \
do { \
if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
common_hash ^= lo_hash_dword >> n; \
else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
bucket_hash ^= lo_hash_dword >> n; \
else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
common_hash ^= hi_hash_dword >> n; \
bucket_hash ^= hi_hash_dword >> n; \
} while (0)
/**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
* @stream: input bitstream to compute the hash on
*
* This function is almost identical to the function above but contains
* several optimizations such as unwinding all of the loops, letting the
* compiler work out all of the conditional ifs since the keys are static
* defines, and computing two keys at once since the hashed dword stream
* will be the same for both keys.
**/
union ixgbe_atr_hash_dword common)
{
/* record the flow_vm_vlan bits as they are a key part to the hash */
/* generate common hash dword */
/* low dword is word swapped version of common */
/* Process bits 0 and 16 */
/*
* delay this because bit 0 of the stream should not be processed
* so we do not add the VLAN until after bit 0 was processed
*/
/* Process remaining 30 bit of the key */
/* combine common_hash result with signature and bucket hashes */
/* return completed signature hash */
return sig_hash ^ bucket_hash;
}
/**
* ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
* @hw: pointer to hardware structure
* @input: unique input dword
* @common: compressed common input dword
* @queue: queue index to direct traffic to
*
* Note that the tunnel bit in input must not be set when the hardware
* tunneling support does not exist.
**/
union ixgbe_atr_hash_dword input,
union ixgbe_atr_hash_dword common,
{
bool tunnel;
DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
/*
* Get the flow_type in order to program FDIRCMD properly
* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
* fifth is FDIRCMD.TUNNEL_FILTER
*/
(IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
switch (flow_type) {
break;
default:
DEBUGOUT(" Error on flow type input\n");
return;
}
/* configure FDIRCMD register */
if (tunnel)
/*
* The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
* is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
*/
return;
}
do { \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
bucket_hash ^= lo_hash_dword >> n; \
bucket_hash ^= hi_hash_dword >> n; \
} while (0)
/**
* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
* @atr_input: input bitstream to compute the hash on
* @input_mask: mask for the input bitstream
*
* This function serves two main purposes. First it applies the input_mask
* to the atr_input resulting in a cleaned up atr_input data stream.
* Secondly it computes the hash and stores it in the bkt_hash field at
* the end of the input byte stream. This way it will be available for
* future use without needing to recompute the hash.
**/
union ixgbe_atr_input *input_mask)
{
u32 i = 0;
/* Apply masks to input data */
for (i = 0; i < 14; i++)
/* record the flow_vm_vlan bits as they are a key part to the hash */
/* generate common hash dword */
for (i = 1; i <= 13; i++)
/* low dword is word swapped version of common */
/* Process bits 0 and 16 */
/*
* delay this because bit 0 of the stream should not be processed
* so we do not add the VLAN until after bit 0 was processed
*/
/* Process remaining 30 bit of the key */
for (i = 1; i <= 15; i++)
/*
* Limit hash to 13 bits since max bucket count is 8K.
* Store result at the end of the input stream.
*/
}
/**
* ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
* @input_mask: mask to be bit swapped
*
* The source and destination port masks for flow director are bit swapped
* in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
* generate a correctly swapped value we need to bit swap the mask and that
* is what is accomplished by this function.
**/
{
}
/*
* These two macros are meant to address the fact that we have registers
* that are either all or in part big-endian. As a result on big-endian
* systems we will end up byte swapping the value to little-endian before
* it is byte swapped again and written to the hardware in the original
* big-endian format.
*/
{
/* mask IPv6 since it is currently not supported */
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/*
* are zero, then assume a full mask for that field. Also assume that
* a VLAN of 0 is unspecified, so mask that out as well. L4type
* cannot be masked out in this implementation.
*
* This also assumes IPv4 only. IPv6 masking isn't supported at this
* point in time.
*/
/* verify bucket hash is cleared on hash generation */
DEBUGOUT(" bucket hash should always be 0 in mask\n");
/* Program FDIRM and verify partial masks */
case 0x0:
case 0x7F:
break;
default:
DEBUGOUT(" Error on vm pool mask\n");
return IXGBE_ERR_CONFIG;
}
case 0x0:
fdirm |= IXGBE_FDIRM_L4P;
return IXGBE_ERR_CONFIG;
}
case IXGBE_ATR_L4TYPE_MASK:
break;
default:
DEBUGOUT(" Error on flow type mask\n");
return IXGBE_ERR_CONFIG;
}
case 0x0000:
/* mask VLAN ID, fall through to mask VLAN priority */
case 0x0FFF:
/* mask VLAN priority */
break;
case 0xE000:
/* mask VLAN ID only, fall through */
case 0xEFFF:
/* no VLAN fields masked */
break;
default:
DEBUGOUT(" Error on VLAN mask\n");
return IXGBE_ERR_CONFIG;
}
case 0x0000:
/* Mask Flex Bytes, fall through */
case 0xFFFF:
break;
default:
DEBUGOUT(" Error on flexible byte mask\n");
return IXGBE_ERR_CONFIG;
}
if (cloud_mode) {
fdirm |= IXGBE_FDIRM_L3P;
case 0x00:
/* Mask inner MAC, fall through */
case 0xFF:
break;
default:
DEBUGOUT(" Error on inner_mac byte mask\n");
return IXGBE_ERR_CONFIG;
}
case 0x0:
/* Mask vxlan id */
break;
case 0x00FFFFFF:
break;
case 0xFFFFFFFF:
break;
default:
return IXGBE_ERR_CONFIG;
}
case 0x0:
/* Mask turnnel type, fall through */
case 0xFFFF:
break;
default:
DEBUGOUT(" Error on tunnel type byte mask\n");
return IXGBE_ERR_CONFIG;
}
/* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
* tunnel.
*/
}
/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
if (!cloud_mode) {
* layout */
/* write both the same so that UDP and TCP use the same mask */
/* also use it for SCTP */
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
break;
default:
break;
}
/* store source and destination IP masks (big-enian) */
}
return IXGBE_SUCCESS;
}
union ixgbe_atr_input *input,
{
DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
if (!cloud_mode) {
/* currently IPv6 is not supported, must be programmed with 0 */
/* record the source address (big-endian) */
/* record the first 32 bits of the destination address
* (big-endian) */
/* record source and destination port (little-endian)*/
}
/* record VLAN (little-endian) and flex_bytes(big-endian) */
if (cloud_mode) {
cloud_type = 0x80000000;
cloud_type |= addr_high;
}
/* configure FDIRHASH register */
/*
* flush all previous writes to make certain registers are
* programmed prior to issuing the command
*/
/* configure FDIRCMD register */
if (queue == IXGBE_FDIR_DROP_QUEUE)
if (err) {
DEBUGOUT("Flow Director command did not complete!\n");
return err;
}
return IXGBE_SUCCESS;
}
union ixgbe_atr_input *input,
{
/* configure FDIRHASH register */
/* flush hash to HW */
/* Query if filter is present */
if (err) {
DEBUGOUT("Flow Director command did not complete!\n");
return err;
}
/* if filter exists in hardware then remove it */
if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
* @hw: pointer to hardware structure
* @input: input bitstream
* @input_mask: mask for the input bitstream
* @soft_id: software index for the filters
* @queue: queue index to direct traffic to
*
* Note that the caller to this function must lock before calling, since the
* hardware writes must be protected from one another.
**/
union ixgbe_atr_input *input,
union ixgbe_atr_input *input_mask,
{
DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
/*
* Check flow_type formatting, and bail out before we touch the hardware
* if there's a configuration issue
*/
case IXGBE_ATR_FLOW_TYPE_IPV4:
return IXGBE_ERR_CONFIG;
}
break;
return IXGBE_ERR_CONFIG;
}
break;
default:
DEBUGOUT(" Error on flow type input\n");
return err;
}
/* program input mask into the HW */
if (err)
return err;
/* program filters to filter memory */
}
/**
* ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
* @val: read value
*
* Performs read operation to Omer analog register specified.
**/
{
DEBUGFUNC("ixgbe_read_analog_reg8_82599");
(reg << 8));
usec_delay(10);
return IXGBE_SUCCESS;
}
/**
* ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
* @hw: pointer to hardware structure
* @reg: atlas register to write
* @val: value to write
*
* Performs write operation to Omer analog register specified.
**/
{
DEBUGFUNC("ixgbe_write_analog_reg8_82599");
usec_delay(10);
return IXGBE_SUCCESS;
}
/**
* @hw: pointer to hardware structure
*
* Starts the hardware using the generic start_hw function
* and the generation start_hw function.
* Then performs revision-specific operations, if any.
**/
{
DEBUGFUNC("ixgbe_start_hw_82599");
if (ret_val != IXGBE_SUCCESS)
goto out;
if (ret_val != IXGBE_SUCCESS)
goto out;
/* We need to run link autotry after the driver loads */
if (ret_val == IXGBE_SUCCESS)
out:
return ret_val;
}
/**
* ixgbe_identify_phy_82599 - Get physical layer module
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
* If PHY already detected, maintains current PHY type in hw struct,
* otherwise executes the PHY detection routine.
**/
{
DEBUGFUNC("ixgbe_identify_phy_82599");
/* Detect PHY if not unknown - returns success if already detected. */
if (status != IXGBE_SUCCESS) {
/* 82599 10GBASE-T requires an external PHY */
return status;
else
}
/* Set PHY type none if no PHY detected */
return IXGBE_SUCCESS;
}
/* Return error if SFP module has been detected but is not supported */
return IXGBE_ERR_SFP_NOT_SUPPORTED;
return status;
}
/**
* ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
* @hw: pointer to hardware structure
*
* Determines physical layer capabilities of the current configuration.
**/
{
DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
case ixgbe_phy_tn:
case ixgbe_phy_cu_unknown:
goto out;
default:
break;
}
switch (autoc & IXGBE_AUTOC_LMS_MASK) {
case IXGBE_AUTOC_LMS_1G_AN:
if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
goto out;
} else
/* SFI mode so read SFP module */
goto sfp_check;
break;
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
goto out;
break;
if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
goto out;
} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
goto sfp_check;
break;
if (autoc & IXGBE_AUTOC_KX_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KR_SUPP)
goto out;
break;
default:
goto out;
break;
}
/* SFP check must be done last since DA modules are sometimes used to
* test KR mode - we need to id KR mode correctly before SFP module.
* Call identify_sfp because the pluggable module may have changed */
out:
return physical_layer;
}
/**
* ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL
*
* Enables the Rx DMA unit for 82599
**/
{
DEBUGFUNC("ixgbe_enable_rx_dma_82599");
/*
* Workaround for 82599 silicon errata when enabling the Rx datapath.
* If traffic is incoming before we enable the Rx unit, it could hang
* the Rx DMA unit. Therefore, make sure the security engine is
* completely disabled prior to enabling the Rx unit.
*/
if (regval & IXGBE_RXCTRL_RXEN)
else
return IXGBE_SUCCESS;
}
/**
* ixgbe_verify_fw_version_82599 - verify FW version for 82599
* @hw: pointer to hardware structure
*
* Verifies that installed the firmware version is 0.6 or higher
* for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
*
* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
* if the FW version is not supported.
**/
{
DEBUGFUNC("ixgbe_verify_fw_version_82599");
/* firmware check is only necessary for SFI devices */
goto fw_version_out;
}
/* get the offset to the Firmware Module block */
"eeprom read at offset %d failed", IXGBE_FW_PTR);
return IXGBE_ERR_EEPROM_VERSION;
}
goto fw_version_out;
/* get the offset to the Pass Through Patch Configuration block */
&fw_ptp_cfg_offset)) {
"eeprom read at offset %d failed",
return IXGBE_ERR_EEPROM_VERSION;
}
goto fw_version_out;
/* get the firmware version */
"eeprom read at offset %d failed",
return IXGBE_ERR_EEPROM_VERSION;
}
if (fw_version > 0x5)
return status;
}
/**
* ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
* @hw: pointer to hardware structure
*
* Returns TRUE if the LESM FW module is present and enabled. Otherwise
* returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
**/
{
DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
/* get the offset to the Firmware Module block */
if ((status != IXGBE_SUCCESS) ||
goto out;
/* get the offset to the LESM Parameters block */
if ((status != IXGBE_SUCCESS) ||
goto out;
/* get the LESM state word */
if ((status == IXGBE_SUCCESS) &&
lesm_enabled = TRUE;
out:
return lesm_enabled;
}
/**
* ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
* fastest available method
*
* @hw: pointer to hardware structure
* @offset: offset of word in EEPROM to read
* @words: number of words
* @data: word(s) read from the EEPROM
*
* Retrieves 16 bit word(s) read from EEPROM
**/
{
DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
/*
* If EEPROM is detected and can be addressed using 14 bits,
* use EERD otherwise use bit bang
*/
data);
else
data);
return ret_val;
}
/**
* ixgbe_read_eeprom_82599 - Read EEPROM word using
* fastest available method
*
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to read
* @data: word read from the EEPROM
*
* Reads a 16 bit word from the EEPROM
**/
{
DEBUGFUNC("ixgbe_read_eeprom_82599");
/*
* If EEPROM is detected and can be addressed using 14 bits,
* use EERD otherwise use bit bang
*/
(offset <= IXGBE_EERD_MAX_ADDR))
else
return ret_val;
}
/**
* ixgbe_reset_pipeline_82599 - perform pipeline reset
*
* @hw: pointer to hardware structure
*
* Reset pipeline by asserting Restart_AN together with LMS change to ensure
**/
{
/* Enable link if disabled in NVM */
if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
}
/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
/* Wait for AN to leave state 0 */
for (i = 0; i < 10; i++) {
msec_delay(4);
break;
}
if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
DEBUGOUT("auto negotiation not completed\n");
goto reset_pipeline_out;
}
/* Write AUTOC register with original LMS field and Restart_AN */
return ret_val;
}
/**
* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
{
DEBUGFUNC("ixgbe_read_i2c_byte_82599");
/* Acquire I2C bus ownership. */
esdp |= IXGBE_ESDP_SDP0;
while (timeout) {
if (esdp & IXGBE_ESDP_SDP1)
break;
msec_delay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource,"
" acquiring I2C bus timeout.\n");
goto release_i2c_access;
}
}
/* Release I2C bus ownership. */
esdp &= ~IXGBE_ESDP_SDP0;
}
return status;
}
/**
* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
{
DEBUGFUNC("ixgbe_write_i2c_byte_82599");
/* Acquire I2C bus ownership. */
esdp |= IXGBE_ESDP_SDP0;
while (timeout) {
if (esdp & IXGBE_ESDP_SDP1)
break;
msec_delay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource,"
" acquiring I2C bus timeout.\n");
goto release_i2c_access;
}
}
/* Release I2C bus ownership. */
esdp &= ~IXGBE_ESDP_SDP0;
}
return status;
}