/*
* CDDL HEADER START
*
* Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include "ixgbe_sw.h"
#include "ixgbe_debug.h"
#ifdef IXGBE_DEBUG
/*
* Dump interrupt-related registers & structures
*/
void
{
int i, j;
/*
* interrupt control registers
*/
/* ivar: interrupt vector allocation registers */
for (i = 0; i < IXGBE_IVAR_REG_NUM; i++) {
}
}
/* each allocated vector */
"vector %d rx rings %d tx rings %d eitr: 0x%x\n",
/* for each rx ring bit set */
while (j >= 0) {
}
/* for each tx ring bit set */
while (j >= 0) {
j, IXGBE_IVAR_TX_QUEUE(j),
}
}
/* reta: RSS redirection table */
for (i = 0; i < 32; i++) {
}
/* rssrk: RSS random key */
for (i = 0; i < 10; i++) {
}
for (i = 0; i < 16; i++) {
}
}
/* check mta */
for (i = 0; i < 128; i++) {
}
}
/* check vfta */
{
for (i = 0; i < 640; i++) {
}
off += 4;
}
}
/* check mdef */
for (i = 0; i < 8; i++) {
}
}
}
/*
* Dump an ethernet address
*/
void
{
}
void
{
int i;
"PCI_CONF_VENID:\t0x%x\n",
"PCI_CONF_DEVID:\t0x%x\n",
"PCI_CONF_COMMAND:\t0x%x\n",
"PCI_CONF_STATUS:\t0x%x\n",
"PCI_CONF_REVID:\t0x%x\n",
"PCI_CONF_PROG_CLASS:\t0x%x\n",
"PCI_CONF_SUB_CLASS:\t0x%x\n",
"PCI_CONF_BAS_CLASS:\t0x%x\n",
"PCI_CONF_CACHE_LINESZ:\t0x%x\n",
"PCI_CONF_LATENCY_TIMER:\t0x%x\n",
"PCI_CONF_HEADER_TYPE:\t0x%x\n",
"PCI_CONF_BIST:\t0x%x\n",
"PCI_CONF_BASE0:\t0x%x\n",
"PCI_CONF_BASE1:\t0x%x\n",
"PCI_CONF_BASE2:\t0x%x\n",
/* MSI-X BAR */
"PCI_CONF_BASE3:\t0x%x\n", msix_bar);
"PCI_CONF_BASE4:\t0x%x\n",
"PCI_CONF_BASE5:\t0x%x\n",
"PCI_CONF_CIS:\t0x%x\n",
"PCI_CONF_SUBVENID:\t0x%x\n",
"PCI_CONF_SUBSYSID:\t0x%x\n",
"PCI_CONF_ROM:\t0x%x\n",
"PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr);
"PCI_CONF_ILINE:\t0x%x\n",
"PCI_CONF_IPIN:\t0x%x\n",
"PCI_CONF_MIN_G:\t0x%x\n",
"PCI_CONF_MAX_L:\t0x%x\n",
/* Power Management */
"PCI_PM_CAP_ID:\t0x%x\n",
"PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr);
"PCI_PM_CAP:\t0x%x\n",
"PCI_PM_CSR:\t0x%x\n",
"PCI_PM_CSR_BSE:\t0x%x\n",
"PCI_PM_DATA:\t0x%x\n",
/* MSI Configuration */
"PCI_MSI_CAP_ID:\t0x%x\n",
"PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr);
"PCI_MSI_CTRL:\t0x%x\n",
"PCI_MSI_ADDR:\t0x%x\n",
"PCI_MSI_ADDR_HI:\t0x%x\n",
"PCI_MSI_DATA:\t0x%x\n",
/* MSI-X Configuration */
"PCI_MSIX_CAP_ID:\t0x%x\n",
"PCI_MSIX_NEXT_PTR:\t0x%x\n", next_ptr);
"PCI_MSIX_CTRL:\t0x%x\n", msix_ctrl);
"PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset);
"PCI_MSIX_TBL_BIR:\t0x%x\n", tbl_bir);
"PCI_MSIX_PBA_OFFSET:\t0x%x\n", pba_offset);
"PCI_MSIX_PBA_BIR:\t0x%x\n", pba_bir);
/* PCI Express Configuration */
"PCIE_CAP_ID:\t0x%x\n",
"PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr);
"PCIE_PCIECAP:\t0x%x\n",
"PCIE_DEVCAP:\t0x%x\n",
"PCIE_DEVCTL:\t0x%x\n",
"PCIE_DEVSTS:\t0x%x\n",
"PCIE_LINKCAP:\t0x%x\n",
"PCIE_LINKCTL:\t0x%x\n",
"PCIE_LINKSTS:\t0x%x\n",
/* MSI-X Memory Space */
return;
}
return;
}
for (i = 0; i <= msix_tbl_sz; i++) {
}
}
/*
* Dump registers
*/
void
{
int i;
DEBUGFUNC("ixgbe_dump_regs");
/* Dump basic's like CTRL, STATUS, CTRL_EXT. */
/* Misc Interrupt regs */
/* Dump RX related reg's */
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
/* Dump TX related regs */
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
#endif