Searched refs:RADEON_WRITE (Results 1 - 4 of 4) sorted by relevance
| /solaris-x11-s11/open-src/kernel/efb/src/ |
| H A D | radeon_cp.c | 871 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
950 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
955 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
957 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
963 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
970 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
972 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
992 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1021 RADEON_WRITE(RADEON_CP_CSQ_CNT
[all...] |
| H A D | radeon_irq.c | 47 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
288 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
303 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
332 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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| H A D | radeon_drv.h | 1023 #define RADEON_WRITE(reg, val) \ macro
1034 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1041 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1179 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); \
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| H A D | radeon_state.c | 2003 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
2005 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
2007 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
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