Lines Matching refs:RADEON_WRITE
871 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
950 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
955 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
957 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
963 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
970 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
972 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
992 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1021 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1046 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1060 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1087 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1096 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1107 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1108 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1136 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1142 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1143 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1156 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1159 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1163 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1169 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1182 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1190 RADEON_WRITE(RADEON_CP_RB_CNTL,
1193 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1207 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1214 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1218 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1221 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1224 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1228 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1233 RADEON_WRITE(RADEON_ISYNC_CNTL,
1251 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1289 RADEON_WRITE(RADEON_CP_RB_CNTL,
1291 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1315 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1338 RADEON_WRITE(RADEON_AIC_CNTL,
1342 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1345 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1346 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start +
1350 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1351 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1353 RADEON_WRITE(RADEON_AIC_CNTL,
1961 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1965 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1966 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1968 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +