1450N/A * Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 1450N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1450N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Gareth Hughes <gareth@valinux.com> 1450N/A * Kevin E. Martin <martin@valinux.com> 1450N/A * Helper functions for client state checking and fixup 1450N/A * Hrm ... the story of the offset ... So this function converts 1450N/A * the various ideas of what userland clients might have for an 1450N/A * offset in the card address space into an offset into the card 1450N/A * address space :) So with a sane client, it should just keep 1450N/A * the value intact and just do some boundary checking. However, 1450N/A * not all clients are sane. Some older clients pass us 0 based 1450N/A * offsets relative to the start of the framebuffer and some may 1450N/A * assume the AGP aperture it appended to the framebuffer, so we 1450N/A * try to detect those cases and fix them up. 1450N/A * Note: It might be a good idea here to make sure the offset lands 1450N/A * in some "allowed" area to protect things like the PCIE GART... 1450N/A * First, the best case, the offset already lands in either the 1450N/A * framebuffer or the GART mapped space 1450N/A * Ok, that didn't happen... now check if we have a zero based 1450N/A * offset that fits in the framebuffer + gart space, apply the 1450N/A * magic offset we get from SETPARAM or calculated from fb_location 1450N/A /* Finally, assume we aimed at a GART offset if beyond the fb */ 1450N/A /* Now recheck and fail if out of bounds */ 1450N/A /* These packets don't contain memory offsets */ 1450N/A /* XXX Are there old drivers needing other packets? */ 1450N/A /* probably safe but will never need them? */ 1450N/A/* these packets are safe */ 1450N/A "Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
1450N/A /* carefully check packet contents */ 1450N/A i++;
/* skip attribute field */ 1450N/A "Invalid offset (k=%d i=%d) ini" 1450N/A " 3D_LOAD_VBPNTR packet.\n", k, i);
1450N/A /* have one more to process, they come in pairs */ 1450N/A "Invalid offset (k=%d i=%d) in" 1450N/A " 3D_LOAD_VBPNTR packet.\n", k, i);
1450N/A /* do the counts match what we expect ? */ 1450N/A "Malformed 3D_LOAD_VBPNTR packet" 1450N/A "(k=%d i=%d narrays=%d count+1=%d).\n",
1450N/A if ((
cmd[
1] &
0x8000ffff) !=
0x80000810) {
1450N/A "Invalid indx_buffer reg address %08X\n",
cmd[
1]);
1450N/A "Invalid indx_buffer offset is %08X\n",
cmd[
2]);
1450N/A /* MSB of opcode: next DWORD GUI_CNTL */ 1450N/A * CP hardware state programming functions 1450N/A * New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 1450N/A * 1.3 cmdbuffers allow all previous state to be updated as well as 1450N/A * the tcl scalar and vector areas. 1450N/A "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
1450N/A "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
1450N/A "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
1450N/A * Performance monitoring functions 1450N/A int x,
int y,
int w,
int h,
int r,
int g,
int b)
1450N/A ((g &
0xfc) <<
3) | ((b &
0xf8) >>
3));
1450N/A color = (((
0xfful) <<
24) | (r <<
16) | (g <<
8) | b);
1450N/A * Collapse various things into a wait flag -- trying to 1450N/A * guess if userspace slept -- better just to have them tell us. 1450N/A /* Purple box for page flipping */ 1450N/A /* Red box if we have to wait for idle at any point */ 1450N/A /* Blue box: lost context? */ 1450N/A /* Yellow box for texture swaps */ 1450N/A /* Green box if hardware never idles (as far as we can tell) */ 1450N/A * Draw bars indicating number of buffers allocated 1450N/A * (not a great measure, easily confused) 1450N/A * CP command dispatch functions 1450N/A * Ensure the 3D stream is idle before doing a 1450N/A * 2D fill to clear the front or back buffer. 1450N/A /* Make sure we restore the 3D state next time. */ 1450N/A * no docs available, based on reverse engeneering 1450N/A * Make sure we restore the 3D state next time. 1450N/A * we haven't touched any "normal" state - still 1450N/A /* FIXME : reverse engineer that for Rx00 cards */ 1450N/A * FIXME : the mask supposedly contains low-res 1450N/A * z values. So can't set just to the max (0xff? 1450N/A * or actually 0x3fff?), need to take z clear 1450N/A * pattern seems to work for r100, though get 1450N/A * slight rendering errors with glxgears. If 1450N/A * hierz is not enabled for r100, only 4 bits 1450N/A * which indicate clear (15,16,31,32, all zero) 1450N/A * matter, the other ones are ignored, and the 1450N/A * same clear mask can be used. That's very 1450N/A * different behaviour than R200 which needs 1450N/A * different clear mask and different number 1450N/A * of tiles to clear if hierz is enabled or not !?! 1450N/A * clear mask : chooses the clearing pattern. 1450N/A * rv250: could be used to clear only parts of macrotiles 1450N/A * (but that would get really complicated...)? 1450N/A * bit 0 and 1 (either or both of them ?!?!) are used to 1450N/A * not clear tile (or maybe one of the bits indicates if 1450N/A * the tile is compressed or not), bit 2 and 3 to not 1450N/A * | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| 1450N/A * bits ------------------------------------------------- 1450N/A * | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| 1450N/A * rv100: clearmask covers 2x8 4x1 tiles, but one clear 1450N/A * still covers 256 pixels ?!? 1450N/A /* what offset is this exactly ? */ 1450N/A /* need ctlstat, otherwise get some strange black flickering */ 1450N/A * it looks like r200 needs rv-style clears, at 1450N/A * least if hierz is not enabled? 1450N/A * FIXME : figure this out for r200 (when hierz 1450N/A * is enabled). Or maybe r200 actually doesn't 1450N/A * need to put the low-res z value into the tile 1450N/A * cache like r100, but just needs to clear the 1450N/A * hi-level z-buffer? Works for R100, both with 1450N/A * hierz and without.R100 seems to operate on 1450N/A * need to be 64 pix (4 blocka) aligned? 1450N/A * Potentially problematic with resolutions 1450N/A * which are not 64 pix aligned? 1450N/A /* the number of tiles to clear */ 1450N/A * chooses the clearing pattern. 1450N/A * (8x2 4x4 z-pixels on rv250) 1450N/A * judging by the first tile 1450N/A * offset needed, could possibly 1450N/A * tiles instead of 8x2 * 4x4 1450N/A * macro tiles, though would 1450N/A * still need clear mask for 1450N/A /* the number of tiles to clear */ 1450N/A * chooses the clearing pattern. 1450N/A /* rv100 might not need 64 pix alignment */ 1450N/A /* offsets are, hmm, weird */ 1450N/A /* the number of tiles to clear */ 1450N/A * chooses the clearing pattern. 1450N/A /* TODO don't always clear all hi-level z tiles */ 1450N/A * r100 and cards without hierarchical z-buffer 1450N/A * have no high-level z-buffer 1450N/A * FIXME : the mask supposedly contains low-res 1450N/A * z values. So can't set just to the max (0xff? 1450N/A * or actually 0x3fff?), need to take z clear value 1450N/A * We have to clear the depth and/or stencil buffers by 1450N/A * rendering a quad into just those buffers. Thus, we have to 1450N/A * make sure the 3D engine is configured correctly. 1450N/A (
/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ 1450N/A /* Vertex format (X, Y, Z, W) */ 1450N/A * Depth buffer specific enables 1450N/A * Stencil buffer specific enables 1450N/A /* Make sure we restore the 3D state next time. */ 1450N/A * Funny that this should be required -- 1450N/A /* Make sure we restore the 3D state next time. */ 1450N/A * Funny that this should be required -- 1450N/A * Increment the clear counter. The client-side 3D driver must 1450N/A * wait on this value before performing the clear ioctl. We 1450N/A * need this because the card's so damned fast... 1450N/A /* Do some trivial performance monitoring... */ 1450N/A * Wait for the 3D stream to idle before dispatching the bitblt. 1450N/A * This will prevent data corruption between the two streams. 1450N/A /* Make this work even if front & back are flipped: */ 1450N/A * Increment the frame counter. The client-side 3D driver must 1450N/A * throttle the framerate by waiting for this value before 1450N/A * performing the swapbuffer ioctl. 1450N/A /* Do some trivial performance monitoring... */ 1450N/A /* Update the frame offsets for both CRTCs */ 1450N/A * Increment the frame counter. The client-side 3D driver must 1450N/A * throttle the framerate by waiting for this value before 1450N/A * performing the swapbuffer ioctl. 1450N/A /* Emit the next cliprect */ 1450N/A /* Emit the vertex buffer rendering commands */ 1450N/A /* Emit the vertex buffer age */ 1450N/A * Indirect buffer data must be an even number of 1450N/A * dwords, so if we've been given an odd number we must 1450N/A * pad the data with a Type-2 CP packet. 1450N/A /* Fire off the indirect buffer */ 1450N/A * Flush the pixel cache. This ensures no pixel data gets mixed 1450N/A * up with the texture data from the host data blit, otherwise 1450N/A * part of the texture image may be corrupted. 1450N/A * The compiler won't optimize away a division by a variable, 1450N/A * even if the only legal values are powers of two. Thus, we'll 1450N/A /* we got tiled coordinates, untile them */ 1450N/A * Make a copy of some parameters in case we have to 1450N/A * update them for a multi-pass texture blit. 1450N/A * Dispatch the indirect buffer. 1450N/A * texture micro tiling in use, minimum texture 1450N/A * width is thus 16 bytes. however, we cannot use 1450N/A * blitter directly for texture width < 64 bytes, 1450N/A * since minimum tex pitch is 64 bytes and we need 1450N/A * this to match the texture width, otherwise the 1450N/A * blitter will tile it wrong. Thus, tiling manually 1450N/A * in this case. Additionally, need to special case 1450N/A * tex height = 1, since our actual image will have 1450N/A * height 2 and we need to ensure we don't read 1450N/A * beyond the texture size from user space. 1450N/A * TODO: make sure this works when not 1450N/A * Texture image width is larger than the 1450N/A * minimum, so we can upload it directly. 1450N/A * Texture image width is less than the minimum, 1450N/A * so we need to pad out each image scanline to 1450N/A /* Update the input parameters for next time */ 1450N/A * Flush the pixel cache after the blit completes. This ensures 1450N/A * the texture data is written out to memory before rendering 1450N/A * Allocates a virtual surface 1450N/A * doesn't always allocate a real surface, will stretch an existing 1450N/A * Note that refcount can be at most 2, since during a free refcount=3 1450N/A * might mean we have to allocate a new surface which might not always 1450N/A * For example : we allocate three contigous surfaces ABC. If B is 1450N/A * freed, we suddenly need two surfaces to store A and C, which might 1450N/A /* make sure there is no overlap with existing surfaces */ 1450N/A /* find a virtual surface */ 1450N/A /* try to reuse an existing surface */ 1450N/A /* okay, we need a new one */ 1450N/A /* we didn't find anything */ 1450N/A /* find the virtual surface */ 1450N/A * Not sure why this isn't set all the time: 1450N/A * Called whenever a client dies, from drm_release. 1450N/A * NOTE: Lock isn't necessarily held when this is called! 1450N/A * Swapping and flipping are different operations, need different ioctls. 1450N/A * They can & should be intermixed to support multiple 3d windows. 1450N/A * Build up a prim_t record: 1450N/A * Build up a prim_t record: 1450N/A * Wait for the 3D stream to idle before the indirect buffer 1450N/A * containing 2D acceleration commands is processed. 1450N/A * Dispatch the indirect buffer full of commands from the 1450N/A * X server. This is insecure and is thus only available to 1450N/A * FIXME The second and subsequent times round 1450N/A * this loop, send a WAIT_UNTIL_3D_IDLE before 1450N/A * calling emit_clip_rect(). This fixes a 1450N/A * lockup on fast machines when sending 1450N/A * several cliprects with a cmdbuf, as when 1450N/A * waving a 2D window over a 3D 1450N/A * window. Something in the commands from user 1450N/A * space seems to hang the card when they're 1450N/A * sent several times in a row. That would be 1450N/A * the correct place to fix it but this works 1450N/A * around it until I can figure that out - Tim 1450N/A * Allocate an in-kernel area and copy in the cmdbuf. Do this 1450N/A * to avoid races between checking values and using those values 1450N/A * in other code, and simply to avoid a lot of function calls 1450N/A /* microcode_version != r300 */ 1450N/A * This ioctl() doesn't work on 64-bit platforms because 1450N/A * hw_lock is a pointer which can't fit into an int-sized 1450N/A * variable. According to Michel Dänzer, the ioctl) is 1450N/A * only used on embedded platforms, so not supporting it 1450N/A * shouldn't be a problem. If the same functionality is 1450N/A * needed on 64-bit platforms, a new ioctl() would have 1450N/A * to be added, so backwards-compatibility for the embedded 1450N/A * platforms can be maintained. --davidm 4-Feb-2004. 1450N/A /* The lock is the first dword in the sarea. */ 1450N/A * - Check for and clean up flipped page state 1450N/A * - Free any alloced GART memory. 1450N/A * - Free any alloced radeon surfaces. 1450N/A * DRM infrastructure takes care of reclaiming dma buffers.