/*
*/
/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
/*
* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*/
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "r300_reg.h"
#include "radeon_io32.h"
/* CP microcode (from ATI) */
{0x21007000, 0000000000},
{0x20007000, 0000000000},
{0x000000ab, 0x00000004},
{0x000000af, 0x00000004},
{0x66544a49, 0000000000},
{0x49494174, 0000000000},
{0x54517d83, 0000000000},
{0x498d8b64, 0000000000},
{0x49494949, 0000000000},
{0x49da493c, 0000000000},
{0x49989898, 0000000000},
{0xd34949d5, 0000000000},
{0x9dc90e11, 0000000000},
{0xce9b9b9b, 0000000000},
{0x000f0000, 0x00000016},
{0x352e232c, 0000000000},
{0x00000013, 0x00000004},
{0x000f0000, 0x00000016},
{0x352e272c, 0000000000},
{0x000f0001, 0x00000016},
{0x3239362f, 0000000000},
{0x000077ef, 0x00000002},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00000016, 0x00000004},
{0x0003802a, 0x00000002},
{0x040067e0, 0x00000002},
{0x00000016, 0x00000004},
{0x000077e0, 0x00000002},
{0x00065000, 0x00000002},
{0x000037e1, 0x00000002},
{0x040067e1, 0x00000006},
{0x000077e0, 0x00000002},
{0x000077e1, 0x00000002},
{0x000077e1, 0x00000006},
{0xffffffff, 0000000000},
{0x10000000, 0000000000},
{0x0003802a, 0x00000002},
{0x040067e0, 0x00000006},
{0x00007675, 0x00000002},
{0x00007676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0003802b, 0x00000002},
{0x04002676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0000002e, 0x00000018},
{0x0000002e, 0x00000018},
{0000000000, 0x00000006},
{0x0000002f, 0x00000018},
{0x0000002f, 0x00000018},
{0000000000, 0x00000006},
{0x01605000, 0x00000002},
{0x00065000, 0x00000002},
{0x00098000, 0x00000002},
{0x00061000, 0x00000002},
{0x64c0603d, 0x00000004},
{0x00080000, 0x00000016},
{0000000000, 0000000000},
{0x0400251d, 0x00000002},
{0x00007580, 0x00000002},
{0x00067581, 0x00000002},
{0x04002580, 0x00000002},
{0x00067581, 0x00000002},
{0x00000046, 0x00000004},
{0x00005000, 0000000000},
{0x00061000, 0x00000002},
{0x0000750e, 0x00000002},
{0x00019000, 0x00000002},
{0x00011055, 0x00000014},
{0x00000055, 0x00000012},
{0x0400250f, 0x00000002},
{0x0000504a, 0x00000004},
{0x00007565, 0x00000002},
{0x00007566, 0x00000002},
{0x00000051, 0x00000004},
{0x01e655b4, 0x00000002},
{0x4401b0dc, 0x00000002},
{0x01c110dc, 0x00000002},
{0x2666705d, 0x00000018},
{0x040c2565, 0x00000002},
{0x0000005d, 0x00000018},
{0x04002564, 0x00000002},
{0x00007566, 0x00000002},
{0x00000054, 0x00000004},
{0x00401060, 0x00000008},
{0x00101000, 0x00000002},
{0x000d80ff, 0x00000002},
{0x00800063, 0x00000008},
{0x000f9000, 0x00000002},
{0x000e00ff, 0x00000002},
{0000000000, 0x00000006},
{0x00000080, 0x00000018},
{0x00000054, 0x00000004},
{0x00007576, 0x00000002},
{0x00065000, 0x00000002},
{0x00009000, 0x00000002},
{0x00041000, 0x00000002},
{0x0c00350e, 0x00000002},
{0x00049000, 0x00000002},
{0x00051000, 0x00000002},
{0x01e785f8, 0x00000002},
{0x00200000, 0x00000002},
{0x00600073, 0x0000000c},
{0x00007563, 0x00000002},
{0x006075f0, 0x00000021},
{0x20007068, 0x00000004},
{0x00005068, 0x00000004},
{0x00007576, 0x00000002},
{0x00007577, 0x00000002},
{0x0000750e, 0x00000002},
{0x0000750f, 0x00000002},
{0x00a05000, 0x00000002},
{0x00600076, 0x0000000c},
{0x006075f0, 0x00000021},
{0x000075f8, 0x00000002},
{0x00000076, 0x00000004},
{0x000a750e, 0x00000002},
{0x0020750f, 0x00000002},
{0x00600079, 0x00000004},
{0x00007570, 0x00000002},
{0x00007571, 0x00000002},
{0x00007572, 0x00000006},
{0x00005000, 0x00000002},
{0x00a05000, 0x00000002},
{0x00007568, 0x00000002},
{0x00061000, 0x00000002},
{0x00000084, 0x0000000c},
{0x00058000, 0x00000002},
{0x0c607562, 0x00000002},
{0x00000086, 0x00000004},
{0x00600085, 0x00000004},
{0x400070dd, 0000000000},
{0x000380dd, 0x00000002},
{0x00000093, 0x0000001c},
{0x00065095, 0x00000018},
{0x040025bb, 0x00000002},
{0x00061096, 0x00000018},
{0x040075bc, 0000000000},
{0x000075bb, 0x00000002},
{0x000075bc, 0000000000},
{0x00090000, 0x00000006},
{0x00090000, 0x00000002},
{0x000d8002, 0x00000006},
{0x00005000, 0x00000002},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x01665000, 0x00000002},
{0x000a0000, 0x00000002},
{0x000671cc, 0x00000002},
{0x0286f1cd, 0x00000002},
{0x000000a3, 0x00000010},
{0x21007000, 0000000000},
{0x000000aa, 0x0000001c},
{0x00065000, 0x00000002},
{0x000a0000, 0x00000002},
{0x00061000, 0x00000002},
{0x000b0000, 0x00000002},
{0x38067000, 0x00000002},
{0x000a00a6, 0x00000004},
{0x20007000, 0000000000},
{0x01200000, 0x00000002},
{0x20077000, 0x00000002},
{0x01200000, 0x00000002},
{0x20007000, 0000000000},
{0x00061000, 0x00000002},
{0x0120751b, 0x00000002},
{0x8040750a, 0x00000002},
{0x8040750b, 0x00000002},
{0x00110000, 0x00000002},
{0x000380dd, 0x00000002},
{0x000000bd, 0x0000001c},
{0x00061096, 0x00000018},
{0x844075bd, 0x00000002},
{0x00061095, 0x00000018},
{0x840075bb, 0x00000002},
{0x00061096, 0x00000018},
{0x844075bc, 0x00000002},
{0x000000c0, 0x00000004},
{0x804075bd, 0x00000002},
{0x800075bb, 0x00000002},
{0x804075bc, 0x00000002},
{0x00108000, 0x00000002},
{0x01400000, 0x00000002},
{0x006000c4, 0x0000000c},
{0x20c07000, 0x00000020},
{0x000000c6, 0x00000012},
{0x00800000, 0x00000006},
{0x0080751d, 0x00000006},
{0x000025bb, 0x00000002},
{0x000040c0, 0x00000004},
{0x0000775c, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460275d, 0x00000020},
{0x00004000, 0000000000},
{0x00007999, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460299b, 0x00000020},
{0x00004000, 0000000000},
{0x01e00830, 0x00000002},
{0x21007000, 0000000000},
{0x00005000, 0x00000002},
{0x00038042, 0x00000002},
{0x040025e0, 0x00000002},
{0x000075e1, 0000000000},
{0x00000001, 0000000000},
{0x000380d9, 0x00000002},
{0x04007394, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
};
{0x21007000, 0000000000},
{0x20007000, 0000000000},
{0x000000b4, 0x00000004},
{0x000000b8, 0x00000004},
{0x6f5b4d4c, 0000000000},
{0x4c4c427f, 0000000000},
{0x5b568a92, 0000000000},
{0x4ca09c6d, 0000000000},
{0xad4c4c4c, 0000000000},
{0x4ce1af3d, 0000000000},
{0xd8afafaf, 0000000000},
{0xd64c4cdc, 0000000000},
{0x4cd10d10, 0000000000},
{0x000f0000, 0x00000016},
{0x362f242d, 0000000000},
{0x00000012, 0x00000004},
{0x000f0000, 0x00000016},
{0x362f282d, 0000000000},
{0x000380e7, 0x00000002},
{0x04002c97, 0x00000002},
{0x000f0001, 0x00000016},
{0x333a3730, 0000000000},
{0x000077ef, 0x00000002},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00000017, 0x00000004},
{0x0003802b, 0x00000002},
{0x040067e0, 0x00000002},
{0x00000017, 0x00000004},
{0x000077e0, 0x00000002},
{0x00065000, 0x00000002},
{0x000037e1, 0x00000002},
{0x040067e1, 0x00000006},
{0x000077e0, 0x00000002},
{0x000077e1, 0x00000002},
{0x000077e1, 0x00000006},
{0xffffffff, 0000000000},
{0x10000000, 0000000000},
{0x0003802b, 0x00000002},
{0x040067e0, 0x00000006},
{0x00007675, 0x00000002},
{0x00007676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0003802c, 0x00000002},
{0x04002676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0000002f, 0x00000018},
{0x0000002f, 0x00000018},
{0000000000, 0x00000006},
{0x00000030, 0x00000018},
{0x00000030, 0x00000018},
{0000000000, 0x00000006},
{0x01605000, 0x00000002},
{0x00065000, 0x00000002},
{0x00098000, 0x00000002},
{0x00061000, 0x00000002},
{0x64c0603e, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00080000, 0x00000016},
{0000000000, 0000000000},
{0x0400251d, 0x00000002},
{0x00007580, 0x00000002},
{0x00067581, 0x00000002},
{0x04002580, 0x00000002},
{0x00067581, 0x00000002},
{0x00000049, 0x00000004},
{0x00005000, 0000000000},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00061000, 0x00000002},
{0x0000750e, 0x00000002},
{0x00019000, 0x00000002},
{0x00011055, 0x00000014},
{0x00000055, 0x00000012},
{0x0400250f, 0x00000002},
{0x0000504f, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007565, 0x00000002},
{0x00007566, 0x00000002},
{0x00000058, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x01e655b4, 0x00000002},
{0x4401b0e4, 0x00000002},
{0x01c110e4, 0x00000002},
{0x26667066, 0x00000018},
{0x040c2565, 0x00000002},
{0x00000066, 0x00000018},
{0x04002564, 0x00000002},
{0x00007566, 0x00000002},
{0x0000005d, 0x00000004},
{0x00401069, 0x00000008},
{0x00101000, 0x00000002},
{0x000d80ff, 0x00000002},
{0x0080006c, 0x00000008},
{0x000f9000, 0x00000002},
{0x000e00ff, 0x00000002},
{0000000000, 0x00000006},
{0x0000008f, 0x00000018},
{0x0000005b, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007576, 0x00000002},
{0x00065000, 0x00000002},
{0x00009000, 0x00000002},
{0x00041000, 0x00000002},
{0x0c00350e, 0x00000002},
{0x00049000, 0x00000002},
{0x00051000, 0x00000002},
{0x01e785f8, 0x00000002},
{0x00200000, 0x00000002},
{0x0060007e, 0x0000000c},
{0x00007563, 0x00000002},
{0x006075f0, 0x00000021},
{0x20007073, 0x00000004},
{0x00005073, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007576, 0x00000002},
{0x00007577, 0x00000002},
{0x0000750e, 0x00000002},
{0x0000750f, 0x00000002},
{0x00a05000, 0x00000002},
{0x00600083, 0x0000000c},
{0x006075f0, 0x00000021},
{0x000075f8, 0x00000002},
{0x00000083, 0x00000004},
{0x000a750e, 0x00000002},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x0020750f, 0x00000002},
{0x00600086, 0x00000004},
{0x00007570, 0x00000002},
{0x00007571, 0x00000002},
{0x00007572, 0x00000006},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00005000, 0x00000002},
{0x00a05000, 0x00000002},
{0x00007568, 0x00000002},
{0x00061000, 0x00000002},
{0x00000095, 0x0000000c},
{0x00058000, 0x00000002},
{0x0c607562, 0x00000002},
{0x00000097, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00600096, 0x00000004},
{0x400070e5, 0000000000},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x000380e5, 0x00000002},
{0x000000a8, 0x0000001c},
{0x000650aa, 0x00000018},
{0x040025bb, 0x00000002},
{0x000610ab, 0x00000018},
{0x040075bc, 0000000000},
{0x000075bb, 0x00000002},
{0x000075bc, 0000000000},
{0x00090000, 0x00000006},
{0x00090000, 0x00000002},
{0x000d8002, 0x00000006},
{0x00007832, 0x00000002},
{0x00005000, 0x00000002},
{0x000380e7, 0x00000002},
{0x04002c97, 0x00000002},
{0x00007820, 0x00000002},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x01200000, 0x00000002},
{0x20077000, 0x00000002},
{0x01200000, 0x00000002},
{0x20007000, 0x00000002},
{0x00061000, 0x00000002},
{0x0120751b, 0x00000002},
{0x8040750a, 0x00000002},
{0x8040750b, 0x00000002},
{0x00110000, 0x00000002},
{0x000380e5, 0x00000002},
{0x000000c6, 0x0000001c},
{0x000610ab, 0x00000018},
{0x844075bd, 0x00000002},
{0x000610aa, 0x00000018},
{0x840075bb, 0x00000002},
{0x000610ab, 0x00000018},
{0x844075bc, 0x00000002},
{0x000000c9, 0x00000004},
{0x804075bd, 0x00000002},
{0x800075bb, 0x00000002},
{0x804075bc, 0x00000002},
{0x00108000, 0x00000002},
{0x01400000, 0x00000002},
{0x006000cd, 0x0000000c},
{0x20c07000, 0x00000020},
{0x000000cf, 0x00000012},
{0x00800000, 0x00000006},
{0x0080751d, 0x00000006},
{0000000000, 0000000000},
{0x0000775c, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460275d, 0x00000020},
{0x00004000, 0000000000},
{0x01e00830, 0x00000002},
{0x21007000, 0000000000},
{0x6464614d, 0000000000},
{0x69687420, 0000000000},
{0x00000073, 0000000000},
{0000000000, 0000000000},
{0x00005000, 0x00000002},
{0x000380d0, 0x00000002},
{0x040025e0, 0x00000002},
{0x000075e1, 0000000000},
{0x00000001, 0000000000},
{0x000380e0, 0x00000002},
{0x04002394, 0x00000002},
{0x00005000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0x00000008, 0000000000},
{0x00000004, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
};
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x000000af, 0x00000008 },
{ 0x000000b3, 0x00000008 },
{ 0x6c5a504f, 0000000000 },
{ 0x4f4f497a, 0000000000 },
{ 0x5a578288, 0000000000 },
{ 0x4f91906a, 0000000000 },
{ 0x4f4f4f4f, 0000000000 },
{ 0x4fe24f44, 0000000000 },
{ 0x4f9c9c9c, 0000000000 },
{ 0xdc4f4fde, 0000000000 },
{ 0xa1cd4f4f, 0000000000 },
{ 0xd29d9d9d, 0000000000 },
{ 0x4f0f9fd7, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x02c0a000, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x00130000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0xc980c045, 0x00000008 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x0000004c, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022056, 0x00000028 },
{ 0x00000056, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a050, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000057, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce063, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x00000063, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x0000005a, 0x00000008 },
{ 0x00802066, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000069, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000085, 0x00000030 },
{ 0x0000005a, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x00012000, 0x00000004 },
{ 0x00082000, 0x00000004 },
{ 0x1800650e, 0x00000004 },
{ 0x00092000, 0x00000004 },
{ 0x000a2000, 0x00000004 },
{ 0x000f0000, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x00000079, 0x00000018 },
{ 0x0000e563, 0x00000004 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x0000006e, 0x00000008 },
{ 0x0000a06e, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000007c, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x0000007c, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0007f, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000089, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x0000008b, 0x00000008 },
{ 0x00c0008a, 0x00000008 },
{ 0x000700e4, 0x00000004 },
{ 0x00000097, 0x00000038 },
{ 0x000ca099, 0x00000030 },
{ 0x080045bb, 0x00000004 },
{ 0x000c209a, 0x00000030 },
{ 0x0800e5bc, 0000000000 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x00120000, 0x0000000c },
{ 0x00120000, 0x00000004 },
{ 0x001b0002, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x000000a7, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x000000ae, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x001400aa, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700e4, 0x00000004 },
{ 0x000000c1, 0x00000038 },
{ 0x000c209a, 0x00000030 },
{ 0x0880e5bd, 0x00000005 },
{ 0x000c2099, 0x00000030 },
{ 0x0800e5bb, 0x00000005 },
{ 0x000c209a, 0x00000030 },
{ 0x0880e5bc, 0x00000005 },
{ 0x000000c4, 0x00000008 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000c8, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000ca, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080c4, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700e1, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
{
return (RADEON_READ(RADEON_CLOCK_CNTL_DATA));
}
{
return (RADEON_READ(RADEON_PCIE_DATA));
}
{
(unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
(unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
(unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
(unsigned int)RADEON_READ(RADEON_AIC_CNTL));
(unsigned int)RADEON_READ(RADEON_AIC_STAT));
(unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
(unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
(unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
}
#endif
/*
* Engine, FIFO control
*/
{
int i;
for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) &
return (0);
}
DRM_UDELAY(1);
}
DRM_ERROR("failed!\n");
#endif
return (EBUSY);
}
{
int i;
for (i = 0; i < dev_priv->usec_timeout; i++) {
return (0);
DRM_UDELAY(1);
}
DRM_ERROR("radeon_do_wait_for_fifo: failed timeout=%d",
#endif
return (EBUSY);
}
{
int i, ret;
if (ret)
return (ret);
for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(RADEON_RBBM_STATUS) &
(void) radeon_do_pixcache_flush(dev_priv);
return (0);
}
DRM_UDELAY(1);
}
DRM_ERROR("radeon_do_wait_for_idle: failed timeout=%d",
#endif
return (EBUSY);
}
/*
* CP control, initialization
*/
/* Load the microcode for the CP */
{
int i;
(void) radeon_do_wait_for_idle(dev_priv);
DRM_INFO("Loading R200 Microcode\n");
for (i = 0; i < 256; i++) {
R200_cp_microcode[i][1]);
R200_cp_microcode[i][0]);
}
DRM_INFO("Loading R300 Microcode\n");
for (i = 0; i < 256; i++) {
R300_cp_microcode[i][1]);
R300_cp_microcode[i][0]);
}
} else {
for (i = 0; i < 256; i++) {
radeon_cp_microcode[i][1]);
radeon_cp_microcode[i][0]);
}
}
}
/*
* Flush any pending commands to the CP. This should only be used just
* prior to a wait for idle, as it informs the engine that the command
* stream is ending.
*/
/*ARGSUSED*/
{
DRM_DEBUG("\n");
#if 0
#endif
}
/* Wait for the CP to go idle. */
int
{
BEGIN_RING(6);
ADVANCE_RING();
COMMIT_RING();
return (radeon_do_wait_for_idle(dev_priv));
}
/* Start the Command Processor. */
{
(void) radeon_do_wait_for_idle(dev_priv);
BEGIN_RING(6);
ADVANCE_RING();
COMMIT_RING();
}
/*
* Reset the Command Processor. This will not flush any pending
* commands, so you must wait for the CP command stream to complete
* before calling this routine.
*/
{
DRM_DEBUG("\n");
}
/*
* Stop the Command Processor. This will not flush any pending
* commands, so you must flush the command stream and wait for the CP
* to go idle before calling this routine.
*/
{
DRM_DEBUG("\n");
dev_priv->cp_running = 0;
}
/* Reset the engine. This will stop the CP if it is running. */
{
DRM_DEBUG("\n");
(void) radeon_do_pixcache_flush(dev_priv);
(void) RADEON_READ(RADEON_RBBM_SOFT_RESET);
(void) RADEON_READ(RADEON_RBBM_SOFT_RESET);
/* Reset the CP ring */
/* The CP is no longer running after an engine reset */
dev_priv->cp_running = 0;
/* Reset any pending vertex, indirect buffers */
return (0);
}
static void
{
/*
* Initialize the memory controller. With new memory map, the fb
* location is not changed, it should have been properly initialized
* already. Part of the problem is that the code below is bogus,
* assuming the GART is always appended to the fb which is not
* necessarily the case
*/
if (!dev_priv->new_memmap)
#if __OS_HAS_AGP
} else
#endif
/* Set the write pointer delay */
/* Initialize the ring buffer's read and write pointers */
#if __OS_HAS_AGP
} else
#endif
{
DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
}
/* Set ring buffer size */
#ifdef _BIG_ENDIAN
#else
#endif
/* Start with assuming that writeback doesn't work */
dev_priv->writeback_works = 0;
/*
* Initialize the scratch register pointer. This will cause
* the scratch register values to be written out to memory
* whenever they are updated.
*
* We simply put this behind the ring read pointer, this works
* with PCI GART as well as (whatever kind of) AGP GART
*/
(RADEON_SCRATCH_REG_OFFSET / sizeof (u32)));
/* Turn on bus mastering */
(void) radeon_do_wait_for_idle(dev_priv);
/* Sync everything up */
}
{
#if 0
/*
* Writeback doesn't seem to work everywhere, test it here and possibly
* enable it if it appears to work
*/
0xdeadbeef)
break;
DRM_UDELAY(1);
}
} else {
dev_priv->writeback_works = 0;
DRM_INFO("writeback test failed\n");
}
if (radeon_no_wb == 1) {
dev_priv->writeback_works = 0;
DRM_INFO("writeback forced off\n");
}
#else
/*
* Writeback doesn't work everywhere. And the timeout is so long
* so Xserver needs more time to start itself. But dtlogin doesn't
* want to wait for the timeout, and it just stops Xserver and
* restart it again. As a result, Xserver cannot start. So, we
* just ignore writeback here.
*/
dev_priv->writeback_works = 0;
#endif
if (!dev_priv->writeback_works) {
/*
* Disable writeback to avoid unnecessary bus master
* transfers
*/
}
}
/* Enable or disable PCI-E GART on the chip */
{
if (on) {
DRM_DEBUG("programming pcie %08X %08lX %08X\n",
} else {
}
}
/* Enable or disable PCI GART on the chip */
{
return;
}
if (on) {
/* set PCI GART page-table base address */
/* set address range for PCI address translate */
/* Turn off AGP aperture -- is this required for PCI GART? */
} else {
}
}
{
/* if we require new memory map but we don't have it fail */
DRM_ERROR("Cannot initialise DRM on this card\n"
"This card requires a new X.org DDX for 3D\n");
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
DRM_DEBUG("Forcing AGP card to PCI mode\n");
DRM_DEBUG("Restoring AGP flag\n");
}
DRM_ERROR("PCI GART memory not allocated!\n");
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
case RADEON_INIT_R200_CP:
break;
case RADEON_INIT_R300_CP:
break;
default:
}
/*
* We don't support anything other than bus-mastering ring mode,
* but the ring can be in either AGP or PCI space for the ring
* read pointer.
*/
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
case 16:
break;
case 32:
default:
break;
}
case 16:
break;
case 32:
default:
break;
}
/*
* longer clear the depth buffer with a 3D rectangle. Hard-code
* all values to prevent unwanted 3D state from slipping through
* and screwing with the clear operation.
*/
UCODE_R100 ? RADEON_ZBLOCK16 : 0));
DRM_GETSAREA();
DRM_ERROR("could not find sarea!\n");
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
DRM_ERROR("could not find cp ring region, offset=0x%lx\n",
init->ring_offset);
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
DRM_ERROR("could not find ring read pointer, offset=0x%lx\n",
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
if (!dev->agp_buffer_map) {
DRM_ERROR("could not find dma buffer region, offset=0x%lx\n",
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
if (init->gart_textures_offset) {
if (!dev_priv->gart_textures) {
DRM_ERROR("could not find GART texture region, "
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
}
#if __OS_HAS_AGP
DRM_ERROR("radeon_do_init_cp: failed to find agp "
"regions,"
"cp_ring=0x%p, ring_rptr=0x%p, agp_buf=0x%p",
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
} else
#endif
{
DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
}
0xffff) << 16;
- dev_priv->fb_location;
/* New let's set the memory map ... */
if (dev_priv->new_memmap) {
DRM_INFO("Setting GART location based on new memory map\n");
/*
* If using AGP, try to locate the AGP aperture at the same
* location in the card and on the bus, though we have to
* align it down.
*/
#if __OS_HAS_AGP
/* Check if valid */
dev_priv->fb_location &&
DRM_INFO("Can't use AGP base @0x%08lx,"
base = 0;
}
}
#endif
/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
if (base == 0) {
0xfffffffful) < base)
}
DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
} else {
DRM_INFO("Setting GART location based on old memory map\n");
}
#if __OS_HAS_AGP
else
#endif
DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
#if __OS_HAS_AGP
/* Turn off PCI GART */
} else
#endif
{
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset) {
DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
} else {
DRM_ERROR("Cannot use PCI Express without "
"GART in FB memory\n");
(void) radeon_do_cleanup_cp(dev);
return (EINVAL);
}
}
DRM_ERROR("failed to init PCI GART!\n");
(void) radeon_do_cleanup_cp(dev);
return (ENOMEM);
}
/* Turn on PCI GART */
}
(void) radeon_do_engine_reset(dev);
return (0);
}
{
/*
* Make sure interrupts are disabled here because the uninstall ioctl
* may not have been called from userspace and after dev_private
* is freed, it's too late.
*/
if (dev->irq_enabled)
(void) drm_irq_uninstall(dev);
#if __OS_HAS_AGP
}
}
}
} else
#endif
{
/* Turn off PCI GART */
DRM_ERROR("failed to cleanup PCI GART!\n");
}
}
}
/* only clear to the start of flags */
return (0);
}
/*
* This code will reinit the Radeon CP hardware after a resume from disc.
* AFAIK, it would be very difficult to pickle the state at suspend time, so
* here we make sure that all Radeon hardware initialisation is re-done without
* affecting running applications.
*
* Charl P. Botha <http://cpbotha.net>
*/
{
if (!dev_priv) {
DRM_ERROR("Called with no initialization\n");
return (EINVAL);
}
DRM_DEBUG("Starting radeon_do_resume_cp()\n");
#if __OS_HAS_AGP
/* Turn off PCI GART */
} else
#endif
{
/* Turn on PCI GART */
}
(void) radeon_do_engine_reset(dev);
DRM_DEBUG("radeon_do_resume_cp() complete\n");
return (0);
}
/*ARGSUSED*/
int
{
#ifdef _MULTI_DATAMODEL
sizeof (init32));
} else {
#endif
#ifdef _MULTI_DATAMODEL
}
#endif
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
case RADEON_CLEANUP_CP:
return (radeon_do_cleanup_cp(dev));
}
return (EINVAL);
}
/*ARGSUSED*/
int
{
if (dev_priv->cp_running) {
return (0);
}
DRM_DEBUG("called with bogus CP mode (%d)\n",
return (0);
}
return (0);
}
/*
* Stop the CP. The engine must have been idled before calling this
* routine.
*/
/*ARGSUSED*/
int
{
int ret;
if (!dev_priv->cp_running)
return (0);
/*
* Flush any pending CP commands. This ensures any outstanding
* commands are executed by the engine before we turn it off.
*/
}
/*
* If we fail to make the engine go idle, we return an error
* code so that the DRM ioctl wrapper can try again.
*/
if (ret)
return (ret);
}
/*
* Finally, we can turn off the CP. If the engine isn't idle,
* we will get some dropped triangles as they won't be fully
* rendered before the CP is shut down.
*/
/* Reset the engine */
(void) radeon_do_engine_reset(dev);
return (0);
}
void
{
int i, ret;
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
#ifdef __linux__
schedule();
#else
"rdnrel", 1);
#else
#if defined(__SOLARIS__) || defined(sun)
(void) drv_usectohz(5);
#else
#endif
#endif
#endif
}
(void) radeon_do_engine_reset(dev);
}
/* Disable *all* interrupts */
/* remove this after permanent addmaps */
for (i = 0; i < RADEON_MAX_SURFACES; i++) {
16 * i, 0);
16 * i, 0);
}
}
/* Free memory heap structures */
/* deallocate kernel resources */
(void) radeon_do_cleanup_cp(dev);
}
}
/* Just reset the CP ring. Called as part of an X Server engine reset. */
/*ARGSUSED*/
int
{
if (!dev_priv) {
DRM_DEBUG("radeon_cp_reset called before init done\n");
return (EINVAL);
}
/* The CP is no longer running after an engine reset */
dev_priv->cp_running = 0;
return (0);
}
/*ARGSUSED*/
int
{
return (radeon_do_cp_idle(dev_priv));
}
/* Added by Charl P. Botha to call radeon_do_resume_cp(). */
/*ARGSUSED*/
int
{
return (radeon_do_resume_cp(dev));
}
/*ARGSUSED*/
int
{
return (radeon_do_engine_reset(dev));
}
/*
* Fullscreen mode
*/
/* KW: Deprecated to say the least: */
/*ARGSUSED*/
int
{
return (0);
}
/*
* Freelist management
*/
/*
* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
* bufs until freelist code is used. Note this hides a problem with
* the scratch register * (used to keep track of last buffer
* completed) being written to before * the last buffer has actually
* completed rendering.
*
* KW: It's also a good way to find free buffers quickly.
*
* KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
* sleep. However, bugs in older versions of radeon_accel.c mean that
* we essentially have to do this, else old clients will break.
*
* However, it does leave open a potential deadlock where all the
* buffers are held by other clients, which can't release them because
* they can't get the lock.
*/
{
int i, t;
int start;
for (t = 0; t < dev_priv->usec_timeout; t++) {
return (buf);
}
start = 0;
}
if (t) {
DRM_UDELAY(1);
}
}
DRM_DEBUG("returning NULL!\n");
return (NULL);
}
#if 0
{
int i, t;
int start;
for (t = 0; t < 2; t++) {
return (buf);
}
}
start = 0;
}
return (NULL);
}
#endif
void
{
int i;
}
}
/*
* CP command submission
*/
int
{
int i;
for (i = 0; i < dev_priv->usec_timeout; i++) {
return (0);
i = 0;
DRM_UDELAY(1);
}
/* FIXME: This return value is ignored in the BEGIN_RING macro! */
DRM_ERROR("failed!\n");
#endif
return (EBUSY);
}
static int
{
int i;
for (i = d->granted_count; i < d->request_count; i++) {
if (!buf)
return (EBUSY); /* NOTE: broken client */
return (EFAULT);
return (EFAULT);
d->granted_count++;
}
return (0);
}
/*ARGSUSED*/
int
{
int ret = 0;
drm_dma_t d;
#ifdef _MULTI_DATAMODEL
} else {
#endif
DRM_COPYFROM_WITH_RETURN(&d, (void *)data, sizeof (d));
#ifdef _MULTI_DATAMODEL
}
#endif
/* Please don't send us buffers. */
if (d.send_count != 0) {
DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
DRM_CURRENTPID, d.send_count);
return (EINVAL);
}
/* We'll send you buffers. */
DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
return (EINVAL);
}
d.granted_count = 0;
if (d.request_count) {
}
#ifdef _MULTI_DATAMODEL
} else {
#endif
DRM_COPYTO_WITH_RETURN((void *)data, &d, sizeof (d));
#ifdef _MULTI_DATAMODEL
}
#endif
return (ret);
}
int
{
int ret = 0;
return (ENOMEM);
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
case CHIP_R200:
case CHIP_R300:
case CHIP_R350:
case CHIP_R420:
case CHIP_RV410:
break;
default:
/* all other chips have no hierarchical z buffer */
break;
}
if (drm_device_is_agp(dev))
else if (drm_device_is_pcie(dev))
else
return (ret);
}
/*
* Create mappings for registers and framebuffer so userland doesn't necessarily
* have to find them.
*/
int
{
int ret;
/* dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; */
if (ret != 0) {
"failed to mmap BAR2 addr=0x%x, len=0x%x",
return (ret);
}
if (ret != 0)
return (ret);
return (0);
}
int
{
DRM_DEBUG("\n");
return (0);
}