Searched refs:intel_ring_emit (Results 1 - 8 of 8) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_ringbuffer.c77 intel_ring_emit(ring, cmd);
78 intel_ring_emit(ring, MI_NOOP);
135 intel_ring_emit(ring, cmd);
136 intel_ring_emit(ring, MI_NOOP);
191 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
192 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
194 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
195 intel_ring_emit(ring, 0); /* low dword */
196 intel_ring_emit(ring, 0); /* high dword */
197 intel_ring_emit(rin
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H A Di915_gem_context.c392 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
394 intel_ring_emit(ring, MI_NOOP);
396 intel_ring_emit(ring, MI_NOOP);
397 intel_ring_emit(ring, MI_SET_CONTEXT);
398 intel_ring_emit(ring, new_context->obj->gtt_offset |
404 intel_ring_emit(ring, MI_NOOP);
407 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
409 intel_ring_emit(ring, MI_NOOP);
H A Dintel_overlay.c256 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
257 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
258 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
259 intel_ring_emit(ring, MI_NOOP);
290 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
291 intel_ring_emit(ring, flip_addr);
345 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
346 intel_ring_emit(ring, flip_addr);
347 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
352 intel_ring_emit(rin
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H A Di915_gem_execbuffer.c730 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
731 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
732 intel_ring_emit(ring, 0);
993 intel_ring_emit(ring, MI_NOOP);
994 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
995 intel_ring_emit(ring, INSTPM);
996 intel_ring_emit(ring, mask << 16 | mode);
H A Dintel_ringbuffer.h270 static inline void intel_ring_emit(struct intel_ring_buffer *ring, function
H A Dintel_display.c7318 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7319 intel_ring_emit(ring, MI_NOOP);
7320 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7322 intel_ring_emit(ring, fb->pitches[0]);
7323 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7324 intel_ring_emit(ring, 0); /* aux display base address, unused */
7359 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7360 intel_ring_emit(ring, MI_NOOP);
7361 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7363 intel_ring_emit(rin
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H A Dintel_pm.c3716 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3717 intel_ring_emit(ring, MI_SET_CONTEXT);
3718 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3723 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3724 intel_ring_emit(ring, MI_NOOP);
3725 intel_ring_emit(ring, MI_FLUSH);
H A Di915_dma.c54 intel_ring_emit(LP_RING(dev_priv), x)

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