Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:intel_ring_emit
77 	intel_ring_emit(ring, cmd);
78 	intel_ring_emit(ring, MI_NOOP);
135 	intel_ring_emit(ring, cmd);
136 	intel_ring_emit(ring, MI_NOOP);
191 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
192 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
194 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
195 	intel_ring_emit(ring, 0); /* low dword */
196 	intel_ring_emit(ring, 0); /* high dword */
197 	intel_ring_emit(ring, MI_NOOP);
204 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
205 	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
206 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
207 	intel_ring_emit(ring, 0);
208 	intel_ring_emit(ring, 0);
209 	intel_ring_emit(ring, MI_NOOP);
259 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
260 	intel_ring_emit(ring, flags);
261 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
262 	intel_ring_emit(ring, 0); /* lower dword */
277 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
278 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
280 	intel_ring_emit(ring, 0);
281 	intel_ring_emit(ring, 0);
297 	intel_ring_emit(ring, MI_NOOP);
299 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
300 	intel_ring_emit(ring, MSG_FBC_REND_STATE);
301 	intel_ring_emit(ring, value);
358 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
359 	intel_ring_emit(ring, flags);
360 	intel_ring_emit(ring, scratch_addr);
361 	intel_ring_emit(ring, 0);
633 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
634 	intel_ring_emit(ring, mmio_offset);
635 	intel_ring_emit(ring, ring->outstanding_lazy_request);
636 	intel_ring_emit(ring, MI_NOOP);
669 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
670 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
671 	intel_ring_emit(ring, ring->outstanding_lazy_request);
672 	intel_ring_emit(ring, MI_USER_INTERRUPT);
717 		intel_ring_emit(waiter,
720 		intel_ring_emit(waiter, seqno);
721 		intel_ring_emit(waiter, 0);
722 		intel_ring_emit(waiter, MI_NOOP);
724 		intel_ring_emit(waiter, MI_NOOP);
725 		intel_ring_emit(waiter, MI_NOOP);
726 		intel_ring_emit(waiter, MI_NOOP);
727 		intel_ring_emit(waiter, MI_NOOP);
736 	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
738 	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
739 	intel_ring_emit(ring__, 0);							\
740 	intel_ring_emit(ring__, 0);							\
762 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
765 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
766 	intel_ring_emit(ring, ring->outstanding_lazy_request);
767 	intel_ring_emit(ring, 0);
780 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
784 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
785 	intel_ring_emit(ring, ring->outstanding_lazy_request);
786 	intel_ring_emit(ring, 0);
998 	intel_ring_emit(ring, MI_FLUSH);
999 	intel_ring_emit(ring, MI_NOOP);
1013 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1014 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1015 	intel_ring_emit(ring, ring->outstanding_lazy_request);
1016 	intel_ring_emit(ring, MI_USER_INTERRUPT);
1130 	intel_ring_emit(ring,
1134 	intel_ring_emit(ring, offset);
1154 		intel_ring_emit(ring, MI_BATCH_BUFFER);
1155 		intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1156 		intel_ring_emit(ring, offset + len - 8);
1157 		intel_ring_emit(ring, MI_NOOP);
1172 		intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1175 		intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1176 		intel_ring_emit(ring, 0);
1177 		intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1178 		intel_ring_emit(ring, cs_offset);
1179 		intel_ring_emit(ring, 0);
1180 		intel_ring_emit(ring, 4096);
1181 		intel_ring_emit(ring, offset);
1182 		intel_ring_emit(ring, MI_FLUSH);
1185 		intel_ring_emit(ring, MI_BATCH_BUFFER);
1186 		intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1187 		intel_ring_emit(ring, cs_offset + len - 8);
1205 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1206 	intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1686 	intel_ring_emit(ring, cmd);
1687 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1688 	intel_ring_emit(ring, 0);
1689 	intel_ring_emit(ring, MI_NOOP);
1705 	intel_ring_emit(ring,
1709 	intel_ring_emit(ring, offset);
1726 	intel_ring_emit(ring,
1730        intel_ring_emit(ring, offset);
1759 	intel_ring_emit(ring, cmd);
1760 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1761 	intel_ring_emit(ring, 0);
1762 	intel_ring_emit(ring, MI_NOOP);