Lines Matching refs:intel_ring_emit
7318 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7319 intel_ring_emit(ring, MI_NOOP);
7320 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7322 intel_ring_emit(ring, fb->pitches[0]);
7323 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7324 intel_ring_emit(ring, 0); /* aux display base address, unused */
7359 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7360 intel_ring_emit(ring, MI_NOOP);
7361 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7363 intel_ring_emit(ring, fb->pitches[0]);
7364 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7365 intel_ring_emit(ring, MI_NOOP);
7400 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7402 intel_ring_emit(ring, fb->pitches[0]);
7403 intel_ring_emit(ring,
7413 intel_ring_emit(ring, pf | pipesrc);
7444 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7446 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7447 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7457 intel_ring_emit(ring, pf | pipesrc);
7510 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7511 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7512 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7513 intel_ring_emit(ring, (MI_NOOP));