Searched refs:LVDS (Results 1 - 4 of 4) sorted by relevance
| /solaris-x11-s11/open-src/kernel/i915/src/ |
| H A D | i915_suspend.c | 213 /* LVDS state */
230 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
281 /* LVDS state */
291 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
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| H A D | intel_lvds.c | 43 /* Private structure for the integrated LVDS support */
99 lvds_reg = LVDS;
121 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
166 /* Set the dithering flag on LVDS as needed, note that there is no
170 /* Bspec wording suggests that LVDS port dithering only exists
270 DRM_ERROR("Can't support LVDS on pipe A\n");
281 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
322 * The LVDS pin pair will already have been turned on in the
329 * Detect the LVDS connection.
331 * Since LVDS does
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| H A D | intel_display.c | 265 /* LVDS 100mhz refclk limits. */
494 * For LVDS just rely on its current settings for dual-channel.
555 * For LVDS just rely on its current settings for dual-channel.
1033 lvds_reg = LVDS;
1296 DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1606 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2948 * unconditionally resets the pll - we need that to have the right LVDS
4447 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4899 * by using the FP0/FP1. In such case we will disable the LVDS
4984 I915_READ(LVDS)
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| H A D | i915_reg.h | 1239 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2085 /* LVDS port control */
2086 #define LVDS 0x61180 macro
2088 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2089 * the DPLL semantics change when the LVDS is assigned to that pipe.
2092 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2096 /* LVDS dithering flag on 965/g4x platform */
2098 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2177 * - LVDS/DVOB/DVOC on
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