Lines Matching refs:LVDS
265 /* LVDS 100mhz refclk limits. */
494 * For LVDS just rely on its current settings for dual-channel.
555 * For LVDS just rely on its current settings for dual-channel.
1033 lvds_reg = LVDS;
1296 DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1606 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2948 * unconditionally resets the pll - we need that to have the right LVDS
4447 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4899 * by using the FP0/FP1. In such case we will disable the LVDS
4984 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5541 * by using the FP0/FP1. In such case we will disable the LVDS
6993 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7079 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7089 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7114 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7124 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8797 * mode changed, e.g. for LVDS where we only change the panel fitter in
9446 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9527 /* Lenovo U160 cannot use SSC on LVDS */
9530 /* Sony Vaio Y cannot use SSC on LVDS */