Searched refs:IMR (Results 1 - 5 of 5) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_ringbuffer.c879 I915_WRITE(IMR, dev_priv->irq_mask);
880 POSTING_READ(IMR);
897 I915_WRITE(IMR, dev_priv->irq_mask);
898 POSTING_READ(IMR);
916 I915_WRITE16(IMR, dev_priv->irq_mask);
917 POSTING_READ16(IMR);
934 I915_WRITE16(IMR, dev_priv->irq_mask);
935 POSTING_READ16(IMR);
H A Di915_suspend.c368 dev_priv->regfile.saveIMR = I915_READ(IMR);
417 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
H A Di915_irq.c806 * IIR bits should never already be set because IMR should
812 * The mask bit in IMR is cleared by dev_priv->rps.work.
2915 I915_WRITE16(IMR, 0xffff);
2935 I915_WRITE16(IMR, dev_priv->irq_mask);
3055 I915_WRITE16(IMR, 0xffff);
3075 I915_WRITE(IMR, 0xffffffff);
3110 /* and unmask in IMR */
3114 I915_WRITE(IMR, dev_priv->irq_mask);
3273 I915_WRITE(IMR, 0xffffffff);
3292 I915_WRITE(IMR,
[all...]
H A Di915_reg.h816 #define IMR 0x020a8 macro
/solaris-x11-s11/open-src/kernel/mdb/modules/
H A Di915.c1367 " IMR:\tInterrupt Mask Register\n"
1420 mdb_printf("Display IMR:\t%08x\n", val);
1442 mdb_printf("Render IMR:\t%08x\n", val);
1454 mdb_printf("PM IMR:\t\t%08x\n", val);
1476 ret = i915_read(dev_priv, (uintptr_t)IMR, &val);

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