Searched refs:phy_addr (Results 1 - 25 of 35) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dcphy.h35 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
37 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
92 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
94 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
126 int phy_addr, struct cphy_ops *phy_ops,
130 phy->addr = phy_addr;
141 struct cphy *(*create)(adapter_t *adapter, int phy_addr,
125 cphy_init(struct cphy *phy, adapter_t *adapter, int phy_addr, struct cphy_ops *phy_ops, struct mdio_ops *mdio_ops) argument
H A Dmv88x201x.c218 static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr, argument
227 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops);
H A Dmy3126.c199 static struct cphy *my3126_phy_create(adapter_t *adapter, int phy_addr, argument
205 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops);
H A Dch_subr.c276 static int fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, argument
289 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
295 static int fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, argument
308 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
359 static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, argument
362 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
377 static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, argument
380 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
406 static int mi1_mdio_ext_readinc(adapter_t *adapter, int phy_addr, int mmd_addr,
409 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
432 mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp) argument
457 mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) argument
1469 int phy_addr = bi->mdio_phybaseaddr + i; local
[all...]
H A Dxpak.c110 static struct cphy *xpak_phy_create(adapter_t * adapter, int phy_addr, argument
H A Dmv88e1xxx.c397 static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr, argument
404 cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops);
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dsis900.c83 static void sis900_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
84 static void amd79c901_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
85 static void ics1893_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
86 static void rtl8201_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
87 static void vt6103_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
93 void (*read_mode) (struct nic *nic, int phy_addr, int *speed, int *duplex);
108 int phy_addr; member in struct:mii_phy
321 int phy_addr; local
373 for (phy_addr = 0; phy_addr < 3
841 sis900_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) argument
890 amd79c901_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) argument
942 ics1893_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) argument
982 rtl8201_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) argument
1026 vt6103_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) argument
[all...]
H A Ddavicom.c213 int i, phy_addr=1;
235 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
258 u16 i, phy_addr=1;
279 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
210 int i, phy_addr=1; local
255 u16 i, phy_addr=1; local
H A De1000.c2841 const uint32_t phy_addr = 1; local
2856 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2894 mdic = ((reg_addr) | (phy_addr << 5) |
2944 const uint32_t phy_addr = 1; local
2960 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2989 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
/illumos-gate/usr/src/uts/common/io/mii/
H A Dmiipriv.h50 uint8_t phy_addr; member in struct:phy_handle
H A Dmii.c281 mh->m_bogus_phy.phy_addr = 0xff;
946 *val = ph->phy_addr;
1067 return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg));
1075 (*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val);
1837 ph->phy_addr = curr_addr;
/illumos-gate/usr/src/uts/common/io/cpqary3/
H A Dcpqary3_talk2ctlr.c441 uint32_t phy_addr; local
684 phy_addr = 0;
686 cmd_size, &phy_addr, cpqary3_phyctgp);
702 cpqary3p->drvr_replyq->replyq_start_paddr = phy_addr;
704 DDI_PUT32_CP(cpqary3p, &perf_cfg->ReplyQAddr0Low32, phy_addr);
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h211 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
212 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
528 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
531 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dbnxe_context.c577 lm_address_t phy_addr = {{0}} ; local
649 phy_addr.as_u32.low = (pdev->hw_info.mem_base[BAR_1].as_u32.low) & 0xfffffff0;
650 phy_addr.as_u32.high = pdev->hw_info.mem_base[BAR_1].as_u32.high;
652 LM_INC64(&phy_addr,(cid*LM_DQ_CID_SIZE));
662 phy_addr,
675 (volatile void *)mm_map_io_space(pdev, phy_addr, LM_DQ_CID_SIZE);
683 DbgMessage(pdev, FATAL, "lm_allocate_cid: mm_map_io_space failed. address low=%d address high=%d\n", phy_addr.as_u32.low,phy_addr.as_u32.high );
H A Dlm_phy.c263 tmp = (pdev->vars.phy_addr << 21) | (reg << 16) | (val & EMAC_MDIO_COMM_DATA) |
337 val = (pdev->vars.phy_addr << 21) | (reg << 16) |
390 u8_t phy_addr,
401 rc = elink_phy_read(&pdev->params.link, phy_addr, dev_addr, reg, ret_val);
418 u8_t phy_addr,
429 rc = elink_phy_write(&pdev->params.link, phy_addr, dev_addr, reg, val);
447 pdev->vars.phy_addr = addr;
388 lm_phy45_read( lm_device_t *pdev, u8_t phy_addr, u8_t dev_addr, u16_t reg, u16_t *ret_val) argument
416 lm_phy45_write( lm_device_t *pdev, u8_t phy_addr, u8_t dev_addr, u16_t reg, u16_t val) argument
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_phy.c3058 u32 phy_addr = 0; local
3064 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3065 hw->phy.addr = phy_addr;
3094 u32 phy_addr = 2; local
3097 phy_addr = 1;
3099 return phy_addr;
3537 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); local
3568 hw->phy.addr = phy_addr;
3646 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); local
3761 u32 phy_addr = 2; local
[all...]
/illumos-gate/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_main.h246 uint64_t phy_addr; member in struct:amd8111s_msgbuf
H A Damd8111s_main.c1000 pRing->msg_buf[msg_idx].phy_addr =
1199 pLayerPointers->pOdl->tx_buf.curr->phy_addr;
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_phy.h156 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
H A Dixgbe_phy.c363 u32 phy_addr; local
376 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
377 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
378 hw->phy.addr = phy_addr;
451 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) argument
458 hw->phy.addr = phy_addr;
/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h472 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
474 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c2625 uint64_t timestamp, phy_addr; local
2924 phy_addr = qlge->ioctl_buf_dma_attr.dma_addr;
2925 if (ql_read_risc_ram(qlge, CODE_RAM_ADDR, phy_addr, CODE_RAM_CNT)
2943 phy_addr = qlge->ioctl_buf_dma_attr.dma_addr;
2944 if (ql_read_risc_ram(qlge, MEMC_RAM_ADDR, phy_addr, MEMC_RAM_CNT)
/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dniu.c135 address.phy_addr = (unm_crbword_t)phy;
/illumos-gate/usr/src/uts/intel/io/dnet/
H A Ddnet.c191 static ushort_t dnet_mii_read(dev_info_t *dip, int phy_addr, int reg_num);
192 static void dnet_mii_write(dev_info_t *dip, int phy_addr, int reg_num,
3819 dnet_mii_read(dev_info_t *dip, int phy_addr, int reg_num) argument
3837 command_word = (uint32_t)phy_addr << MII_PHY_ADDR_ALIGN;
3869 dnet_mii_write(dev_info_t *dip, int phy_addr, int reg_num, int reg_dat) argument
3881 command_word = ((uint32_t)phy_addr << MII_PHY_ADDR_ALIGN);
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_mac_hw.h1324 uint32_t phy_addr : 5; member in struct:_mif_cfg_t::__anon8403::__anon8404
1336 uint32_t phy_addr : 5;

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