/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_MAC_NXGE_MAC_HW_H
#define _SYS_MAC_NXGE_MAC_HW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
/* -------------------------- From May's template --------------------------- */
/* Hardware reset */
typedef enum {
} nxge_reset_t;
/* linkup */
/* Number of multicast filter regs */
/* -------------------------------------------------------------------------- */
#define XMAC_PORT_0 0
/*
* Neptune port PHY type and Speed encoding.
*
* Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits
* speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed
* and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the
* speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy
* type encoding for the ports 0 thru 3.
*
* p3phy p2phy p1phy p0phy p3spd p2spd p1spd p0spd
* | | | | | | | |
* --- --- --- --- --- --- --- ---
* / \ / \ / \ / \ / \ / \ / \ / \
* 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
*/
#define NXGE_PORT_SPD_SHIFT 0
/*
* "xgc" as a possible value for the device property "phy-type"
* was intended for the portmode == PORT_10G_COPPER case. But
* the first 10G copper network I/O device available is the
* TN1010 based copper XAUI card and we use PORT_10G_TN1010 or
* PORT_1G_TN1010 as the portmode, so PORT_10G_COPPER is never
* used as portmode. The driver code related to PORT_10G_COPPER
* is kept in the driver as a place holder for possble future
* 10G copper devices.
*/
(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
/* The speed of TN1010 will be determined by each nxge instance */
(NXGE_PHY_NONE << NXGE_PHY_SHIFT))
(NXGE_PHY_RSVD << NXGE_PHY_SHIFT))
/* Network Modes */
typedef enum nxge_network_mode {
typedef enum nxge_port {
} nxge_port_t;
typedef enum nxge_port_mode {
typedef enum nxge_linkchk_mode {
typedef enum {
typedef enum {
typedef enum {
} xcvr_inuse_t;
/* macros for port offset calculations */
/* XMAC address macros */
#define XMAC_ADDR_OFFSET_0 0
/* BMAC address macros */
/* PCS address macros */
((port_num <= 1) ? \
/* XPCS address macros */
/* ESR address macro */
/* MIF address macros */
/* BMAC registers offset */
/* cfg register bitmap */
typedef union _btxmac_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _brxmac_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _bxif_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* (own da, add filter, fc) */
/* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */
/* XMAC registers offset */
/* xmac config bit fields */
typedef union _xmac_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */
/* MIF registers offset */
/* PCS registers offset */
/* ESR registers offset */
#define ESR_RESET_REG 0
/* Reset Register */
/* Tx MAC Status Register */
/* Rx MAC Status Register */
/* MAC Control Status Register */
/* Tx MAC Configuration Register */
/* Rx MAC Configuration Register */
/* MAC Control Configuration Register */
/* MAC XIF Configuration Register */
/* MAC IPG Registers */
/* MAC Max Frame Size Register */
#define BMAC_MAX_FRAME_SHIFT 0
/* MAC Preamble size register */
/* # of preable bytes TxMAC sends at the beginning of each frame */
/*
* mac address registers:
* register contains comparison
* -------- -------- ----------
* 0 16 MSB of primary MAC addr [47:32] of DA field
* 1 16 middle bits "" [31:16] of DA field
* 2 16 LSB "" [15:0] of DA field
* 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field
* 4*x 16 middle bits "" [31:16]
* 5*x 16 LSB "" [15:0]
* 42 16 MSB of MAC CTRL addr [47:32] of DA.
* 43 16 middle bits "" [31:16]
* 44 16 LSB "" [15:0]
* MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
* if there is a match, MAC will set the bit for alternative address
* filter pass [15]
*
* here is the map of registers given MAC address notation: a:b:c:d:e:f
* ab cd ef
* primary addr reg 2 reg 1 reg 0
* alt addr 1 reg 5 reg 4 reg 3
* alt addr x reg 5*x reg 4*x reg 3*x
* | | | |
* | | | |
* alt addr 7 reg 23 reg 22 reg 21
* ctrl addr reg 44 reg 43 reg 42
*/
/* hash table registers */
/* 27-bit register has the current state for key state machines in the MAC */
#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
/* MAC Host Info Table Registers */
/*
* ********************* XMAC registers *********************************
*/
/* Reset Register */
/* XTX MAC Status Register */
/* XRX MAC Status Register */
/* XMAC Configuration Register */
/* XTX MAC config bits */
/* XRX MAC config bits */
/* MAC transceiver (XIF) configuration registers */
/* IPG register */
#define XMAC_IPG_VALUE_SHIFT 0
#define XMAC_MIN_TX_FRM_SZ_SHIFT 0
/* State Machine Register */
#define XMAC_SM_TX_LNK_MGMT_SHIFT 0
/* Internal Signals 1 Register */
#define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0
/* Internal Signals 2 Register */
#define XMAC_IS2_TX_HB_TIMER_SHIFT 0
/* Register size masking */
/* Alternate MAC address registers */
/* Max / Min parameters for Neptune MAC */
/* HostInfo entry for the unique MAC address */
#define BMAC_UNIQUE_HOST_INFO_ENTRY 0
/* HostInfo entry for the multicat address */
/* XMAC Host Info Register */
typedef union hostinfo {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} hostinfo_t;
/*
* ******************** MIF registers *********************************
*/
/*
* 32-bit register serves as an instruction register when the MIF is
* programmed in frame mode. load this register w/ a valid instruction
* (as per IEEE 802.3u MII spec). poll this register to check for instruction
* execution completion. during a read operation, this register will also
* contain the 16-bit data returned by the transceiver. unless specified
* otherwise, fields are considered "don't care" when polling for
* completion.
*/
/* dev addr in Cl 45 */
/* Clause 45 frame field values */
#define FRAME45_ST 0
#define FRAME45_OP_ADDR 0
typedef union _mif_frame_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_frame_t;
/* used to decide if Cl 22 */
/* or Cl 45 frame is */
/* constructed. */
/* 1 = Clause 45,ST = '00' */
/* 0 = Clause 22,ST = '01' */
typedef union _mif_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_cfg_t;
typedef union _mif_poll_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _mif_poll_mask_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _mif_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_stat_t;
/* MIF State Machine Register */
#define MIF_SM_EXECUTION_SHIFT 0
/*
* ******************** PCS registers *********************************
*/
/* PCS Registers */
typedef union _pcs_ctrl_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_ctrl_t;
typedef union _pcs_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_stat_t;
typedef union _pcs_anar_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _pcs_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* used for diagnostic purposes. bits 20-22 autoclear on read */
#define PCS_SM_TX_STATE_SHIFT 0
typedef union _pcs_stat_mc_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/*
* control which network interface is used. no more than one bit should
* be set.
*/
/*
* ******************** XPCS registers *********************************
*/
/* XPCS Base 10G Control1 Register */
typedef union _xpcs_ctrl1_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_ctrl1_t;
/* XPCS Base 10G Status1 Register (Read Only) */
typedef union _xpcs_stat1_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat1_t;
/* XPCS Base Speed Ability Register. Indicates 10G capability */
typedef union _xpcs_speed_ab_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base 10G Devices in Package Register */
typedef union _xpcs_dev_in_pkg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base 10G Control2 Register */
typedef union _xpcs_ctrl2_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_ctrl2_t;
/* XPCS Base10G Status2 Register */
typedef union _xpcs_stat2_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat2_t;
/* XPCS Base10G Status Register */
typedef union _xpcs_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat_t;
/* XPCS Base10G Test Control Register */
#define TEST_PATTERN_HIGH_FREQ 0
typedef union _xpcs_test_ctl_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base10G Diagnostic Register */
#define XPCS_DIAG_EB_DESKEW_LOSS 0
#define XPCS_DIAG_SYNC_LOSS_SYNC 0
#define XPCS_RX_SM_FAULT_STATE 0
typedef union _xpcs_diag_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_diag_t;
/* XPCS Base10G Tx State Machine Register */
#define XPCS_TX_SM_SEND_DATA 0
/* XPCS Base10G Configuration Register */
typedef union _xpcs_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base10G Mask1 Register */
/* XPCS Base10G Packet Counter */
#define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0
/* XPCS Base10G TX State Machine status register */
/* XPCS Base10G Lane symbol error counters */
/* ESR Reset Register */
/* ESR Configuration Register */
/* ESR Neptune Serdes PLL Configuration */
/* ESR Neptune Serdes Control Register */
(0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_3_SHIFT))
/* ESR Neptune Serdes Test Configuration Register */
#define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0
/* ESR Neptune Ethernet RGMII Configuration Register */
/* ESR Internal Signals Observation Register */
/* ESR Debug Selection Register */
/* ESR Test Configuration Register */
/* convert values */
#define NXGE_BASE(x, y) \
{ \
}
#ifdef __cplusplus
}
#endif
#endif /* _SYS_MAC_NXGE_MAC_HW_H */