d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* CLC Call backs functions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* CLC device structure */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_reg_wb_write(struct elink_dev *cb, u32 offset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_reg_wb_read(struct elink_dev *cb, u32 offset,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* mode - 0( LOW ) /1(HIGH)*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u8 elink_cb_gpio_write(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u8 elink_cb_gpio_mult_write(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u32 elink_cb_gpio_read(struct elink_dev *cb, u16 gpio_num, u8 port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u8 elink_cb_gpio_int_write(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u32 elink_cb_fw_command(struct elink_dev *cb, u32 command, u32 param);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_udelay(struct elink_dev *cb, u32 microsecond);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* This function is called every 1024 bytes downloading of phy firmware.
d14abf155341d55053c76eeec58b787a456b753bRobert MustacchiDriver can use it to print to screen indication for download progress */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_download_progress(struct elink_dev *cb, u32 cur, u32 total);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Each log type has its own parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* u8 port, const char* vendor_name, const char* vendor_pn */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_LOG_ID_OVER_CURRENT = 1, /* u8 port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* u8 port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_LOG_ID_NON_10G_MODULE = 4, /* u8 port */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_event_log(struct elink_dev *cb, const elink_log_id_t log_id, ...);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_load_warpcore_microcode(void);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern u8 elink_cb_path_id(struct elink_dev *cb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_notify_link_changed(struct elink_dev *cb);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /*ELINK_AUX_POWER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Debug prints */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P0(cb, fmt) DbgMessage(cb, WARNelink, fmt)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P1(cb, fmt, arg1) DbgMessage(cb, WARNelink, fmt, arg1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) DbgMessage(cb, WARNelink, fmt, arg1, arg2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi DbgMessage(cb, WARNelink, fmt, arg1, arg2, arg3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_dbg(struct elink_dev *cb, _In_ char *fmt);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_dbg1(struct elink_dev *cb, _In_ char *fmt, u32 arg1);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_dbg2(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiextern void elink_cb_dbg3(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P0(cb, fmt) elink_cb_dbg(cb, fmt)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P1(cb, fmt, arg1) elink_cb_dbg1(cb, fmt, arg1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) elink_cb_dbg2(cb, fmt, arg1, arg2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif // _VBD_
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Single Media board contains single external phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Dual Media board contains two external phy with different media */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DUAL_MEDIA(params) (params->num_phys == 3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Same configuration is shared between the XGXS and the first external phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* elink_phy struct */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Defines the required arguments and function per phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef u8 (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef u8 (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef void (*link_reset_t)(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef void (*config_loopback_t)(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef void (*set_link_led_t)(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchitypedef void (*phy_specific_func_t)(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Loaded during init */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* No Over-Current detection */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Fan failure detection required */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Initialize first the XGXS and only then the phy itself */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* preemphasis values for the rx side */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* preemphasis values for the tx side */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* EMAC address for access MDIO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_100baseT_Half (1<<2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_100baseT_Full (1<<3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_1000baseT_Full (1<<4)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_2500baseX_Full (1<<5)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_10000baseT_Full (1<<6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The address in which version is located*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Called per phy/port init, and it configures LASI, speed, autoneg,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi duplex, flow control negotiation, etc. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Called due to interrupt. It determines the link, speed */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Called when driver is unloading. Should reset the phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set the loopback configuration for the phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Format the given raw number into str up to len */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Reset the phy (both ports) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Set link led mode (on/off/oper)*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* PHY Specific tasks */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Inputs parameters to the CLC */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Default / User Configuration */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Device parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* shmem parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Phy register parameter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* features */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Will be populated during common init */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Will be populated during common init */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Used to configure the EEE Tx LPI timer, has several modes of
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * operation, according to bits 29:28 -
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2'b00: Timer will be configured by nvram, output will be the value
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * from nvram.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2'b01: Timer will be configured by nvram, output will be in
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * microseconds.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2'b10: bits 1:0 contain an nvram value which will be used instead
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * of the one located in the nvram. Output will be that value.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * 2'b11: bits 19:0 contain the idle timer in microseconds; output
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * will be in microseconds.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 hw_led_mode; /* part of the hw_config read from the shmem */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* Device pointer passed to all callback functions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi req_flow_ctrl is set to AUTO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The same definitions as the shmem2 parameter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Output parameters */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 phy_link_up; /* internal phy link indication */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* The same definitions as the shmem parameter */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Functions */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/***********************************************************/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Reset the link. Should be called when driver or interface goes down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi Before calling phy firmware upgrade, the reset_ext_phy should be set
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* elink_link_update should be called upon link interrupt */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* use the following phy functions to read/write from external_phy
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi In order to use it to read/write internal phy registers, use
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi the register */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Reads the link_status from the shmem,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi and update the link vars accordingly */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_link_status_update(struct elink_params *input,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* returns string representing the fw_version of the external phy */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi Basically, the CLC takes care of the led for the link, but in case one needs
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_set_led(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_vars *vars, u8 mode, u32 speed);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* elink_handle_module_detect_int should be called upon module detection
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_handle_module_detect_int(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi otherwise link is down*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* One-time initialization for external phy after power up */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[],
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 shmem2_base_path[], u32 chip_id, u8 one_port_enabled);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Reset the external PHY using GPIO */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Reset the external of SFX7101 */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_hw_reset_phy(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Check swap bit and adjust PHY order */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu32 elink_phy_selection(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Probe the phys on board, and populate them in "params" */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_phy_probe(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Checks if fan failure detection is required on one of the phys on board */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu8 elink_fan_failure_det_req(struct elink_dev *cb, u32 shmem_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Open / close the gate between the NIG and the BRB */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_set_rx_filter(struct elink_params *params, u8 en);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_COMMON_INIT */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* DCBX structs */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Number of maximum COS per chip */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* PFC port configuration params */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* ETS port configuration params */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * valid values are 0 - 5. 0 is highest strict priority.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * There can't be two COS's with the same pri.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u8 num_of_cos; /* Number of valid COS entries*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * when link is already up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_update_pfc(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi struct elink_nig_brb_pfc_port_params *pfc_params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Used to configure the ETS to disable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_disabled(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Used to configure the ETS to BW limited */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Used to configure the ETS to strict */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Configure the COS to ETS according to BW and SP settings.*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_ets_e3b0_config(const struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Read pfc statistic*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi u32 chip_id, u32 shmem_base, u32 shmem2_base,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_sfp_module_detection(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_period_func(struct elink_params *params, struct elink_vars *vars);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_check_half_open_conn(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_enable_pmd_tx(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_pre_init_phy(struct elink_dev *cb,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* EXCLUDE_FROM_BNX2X */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_adjust_phy_func_ptr(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchielink_status_t elink_get_phy_temperature(struct elink_params *params,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiu8 elink_phy_is_temperature_support(struct elink_params *params);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiint get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchiint elink_warpcore_get_sigdet(struct elink_phy *phy,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchivoid elink_force_link(struct elink_params *params, int enable);
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif /* __ELINK_H */